1.5T SONOS Flash Memory Gate Structure Manufacturing
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Solution Overview
Problem
The existing manufacturing processes for 1.5T SONOS flash memory are complex and costly due to the need for additional photomasks and processes to correctly form gate dielectrics and shapes, which also affect device performance by interacting with logic device manufacturing.
Innovation Solution
A method involving a semiconductor substrate with a field oxide layer, well implantation, gate oxide layer formation, and sequential deposition of polysilicon and ONO layers, followed by planarization and photolithography/etching processes to define and form memory and logic device gate structures, reducing the number of required photomasks and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional photomasks and processes are used to correctly form gate dielectrics and shapes, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the gate dielectric layer (ONO layer) and second polysilicon gate layer in the memory gate formation area before the memory gate etching process. This preliminary deposition ensures that when etching occurs, the gate dielectric is already in place and protected, eliminating the need for additional photomasks and processes to form gate dielectrics after etching. The preliminary action resolves the contradiction by achieving precise gate dielectric formation without increasing process complexity.
2Manufacturing precision
If additional photomasks and processes are used to correctly form gate dielectrics and shapes, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of gate dielectrics and gate structures into a single integrated process flow. By depositing the ONO layer and second polysilicon gate layer simultaneously across both memory gate and logic device areas before selective etching, the patent combines multiple operations into one cohesive sequence. This merging eliminates the need for separate photomask steps for gate dielectric formation, thereby achieving precise gate shape formation while reducing manufacturing cost.
3Adaptability or versatility
If the 1.5T SONOS device process interacts with logic device manufacturing, then device performance is affected, but process integration is achieved
Solution Approach 1:
The patent applies segmentation by dividing the substrate into distinct memory gate formation areas and logic device formation areas, separated by isolation structures. This spatial segmentation allows independent optimization of processes for each device type. The memory gate area receives specific treatments (cleaning away gate oxide, depositing ONO and second polysilicon) while logic device areas follow standard CMOS processes. This segmentation decouples the 1.5T SONOS device process from logic device manufacturing, preventing performance degradation while maintaining overall process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and improves device performance by decoupling the 1.5T SONOS device process from logic device manufacturing, thereby enhancing overall efficiency and reliability.
Implementation Method 1
forming a field oxide layer on the semiconductor substrate, isolating to form a plurality of active regions
Implementation Method 2
sequentially depositing an ONO layer and a second polysilicon gate layer
Implementation Method 3
sequentially depositing an ONO layer and a second polysilicon gate layer
Implementation Method 4
defining a position of a memory gate by means of a photolithography process
Implementation Method 5
etching away the first polysilicon gate layer in the area of the position of the memory gate
Implementation Method 6
etching away the first polysilicon gate layer in the area of the position of the memory gate
Implementation Method 7
performing a planarization process on the second polysilicon gate layer
Data Source
AI summary
Embodiments described herein relate to a method for manufacturing a 1.5T SONOS flash memory. First, a first polysilicon gate layer is deposited and formed on a semiconductor substrate, then a formation area of a memory gate is defined on the first polysilicon gate layer, polysilicon in the formation area of the memory gate is etched away, and etching is stopped on a gate oxide layer. Next, an ONO layer and a second polysilicon gate layer are sequentially deposited, chemical mechanical polishing is performed on the second polysilicon gate layer, the ONO layer remaining on the top of the first polysilicon gate layer is cleaned away, and then gate structures of a logic device and a 1.5T SONOS device are formed at the same time.