Epitaxial Silicon Solid-State Image Sensor Manufacturing
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Solution Overview
Problem
Conventional solid-state image sensors using silicon-on-insulator (SOI) substrates face challenges with variations in resistivity and substrate thickness, leading to fixed pattern noise and image degradation due to the use of Czochralski (CZ) grown silicon wafers, which result in non-uniform impurity concentration and crystal defects.
Innovation Solution
A manufacturing method using epitaxial growth to form single crystal silicon layers on SOI wafers, eliminating the need for CZ grown silicon, thereby reducing impurity concentration variations and crystal defects, and incorporating a defect layer formed by ion implantation to control thickness and improve bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Czochralski (CZ) grown silicon wafers are used to manufacture SOI substrates, then substrate thickness can be controlled, but resistivity variations and crystal defects occur leading to fixed pattern noise
Solution Approach 1:
The patent changes the material parameter from CZ grown silicon to epitaxial silicon, which fundamentally alters the impurity concentration profile and crystal structure quality. Epitaxial silicon provides uniform low-resistivity substrate with fewer crystal defects, eliminating the fixed pattern noise while maintaining thickness control capability through the epitaxial growth process parameters.
Solution Approach 2:
The patent introduces a sacrificial defect layer created by ion implantation that is intentionally designed to be removed. This defect layer serves as a temporary structure during manufacturing to enable precise thickness control and bonding, then is discarded in the final product. The defect layer is created by implanting ions to a specific depth, forming a removable sacrificial material that facilitates the separation and thinning processes.
2Length of moving object
If conventional thinning methods (polishing or etching) are used on silicon substrates, then substrate thickness is reduced to 10 μm or less, but uniformity of thickness reduction is poor
Solution Approach 1:
The patent performs preliminary actions by forming the defect layer through ion implantation before the thinning process. This defect layer is created at a controlled depth and serves as a reference for subsequent thickness reduction. The preliminary formation of this sacrificial layer enables more precise and uniform thickness control during the thinning process compared to direct polishing or etching of the bulk substrate.
Solution Approach 2:
The defect layer acts as an intermediary structure between the bulk substrate and the final thin substrate. It facilitates the thinning process by providing a controlled separation plane and reference for thickness uniformity. The defect layer mediates the transition from thick substrate to thin substrate, enabling more precise thickness control than direct thinning methods.
3Productivity
If pixel size is reduced to increase the number of pixels, then aperture ratio of light-receiving region reduces due to transfer gate and interconnects occupying more area
Solution Approach 1:
The patent changes the substrate resistivity parameter by using epitaxial silicon instead of CZ grown silicon. This creates a low-resistivity substrate that allows for more efficient charge collection and reduced noise, enabling smaller pixel sizes to be viable. The uniform low-resistivity material improves the signal-to-noise ratio, making it feasible to reduce pixel size while maintaining aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents fixed pattern noise and enhances image quality by reducing substrate resistivity variations and degradation, allowing for more precise thinning and improved image sensitivity in solid-state image sensors.
Implementation Method 1
forming a single crystal silicon layer on a silicon-on-insulator (SOI) wafer
Implementation Method 2
incorporating a defect layer formed by ion implantation to control thickness and improve bonding strength
Data Source
AI summary
A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.