Two-Step Selective Epitaxial Growth for Elevated Source/Drain Regions
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Solution Overview
Problem
As semiconductor memory devices become denser and gate patterns narrower, the short channel effect becomes more prevalent, and existing elevated source/drain regions with a lightly doped drain (LDD) structure or selective epitaxial growth (SEG) processes fail to adequately suppress this effect due to facet generation and deep impurity implantation at the edges of the source/drain regions.
Innovation Solution
A method involving a two-step selective epitaxial growth (SEG) process where a first layer is formed at a higher temperature and a second layer at a lower temperature, reducing facet incidence and allowing for uniform doping without deep impurity implantation, thereby forming elevated source/drain regions with improved interface characteristics and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second SEG process is carried out at a high temperature to improve elevated source/drain region properties, then the electrical characteristics are improved, but facet generation increases at the upper edge portions
Solution Approach 1:
The elevated source/drain region formation is divided into two separate SEG processes: a first SEG process at high temperature to form the lower portion with good electrical characteristics, and a second SEG process at low temperature to form the upper portion without facet generation. This segmentation allows each process to be optimized for its specific function, resolving the contradiction between electrical performance and shape quality.
Solution Approach 2:
The invention changes the temperature parameter between the two SEG processes. The first SEG is performed at a high temperature (e.g., 700-900°C) to achieve good electrical characteristics in the lower portion, while the second SEG is performed at a low temperature (e.g., 400-700°C) to prevent facet generation in the upper portion. This parameter change strategy allows optimization of different regions for different requirements.
2Quantity of substance
If impurities are implanted into elevated source/drain regions with facets, then doping is achieved, but deep impurity implantation occurs through facets causing short channel effect
Solution Approach 1:
The second SEG process is performed as a preliminary action before impurity implantation to create a facet-free upper surface of the elevated source/drain regions. This preliminary formation of a smooth surface prevents subsequent deep impurity implantation during doping, thereby suppressing the short channel effect while still achieving the required impurity concentration for proper device operation.
3Productivity
If gate pattern width is reduced to increase device density, then integration density improves, but short channel effect increases
Solution Approach 1:
The invention creates different quality characteristics in different portions of the source/drain regions. The lower portion has high impurity concentration for good electrical contact, while the upper portion has low impurity concentration and smooth surface to prevent short channel effect. This local quality differentiation allows the device to maintain high integration density with narrow gate patterns while suppressing short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively suppresses the short channel effect by minimizing facet generation and deep impurity implantation, enhancing the electrical reliability and performance of semiconductor memory devices with gate patterns narrower than 0.35 μm.
Implementation Method 1
A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature.
Data Source
AI summary
Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.