Vertical Bipolar Transistor for RRAM Cell Size Reduction
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Solution Overview
Problem
Conventional resistive random access memory (RRAM) cells have limited capacity due to high series resistance in semiconductor wells, which increases memory cell size and requires silicidation processes that can short-circuit unless spacers are used, thereby increasing cell size further.
Innovation Solution
A vertical bipolar transistor structure is developed with a stack of dielectric and conductive layers, where the first and second conduction terminals and control terminal are formed as semiconductor regions with specific dopant profiles, allowing for reduced memory cell size by minimizing the distance between cells without the need for spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistor structure with doped well is used, then control terminal can be formed, but series resistance is too high requiring silicidation which needs spacers increasing cell size
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical bipolar transistor structure. The conduction terminals and control terminal are arranged vertically with the control terminal positioned between the conduction terminals in the vertical direction, eliminating the need for lateral spacers and reducing memory cell area while maintaining electrical performance
Solution Approach 2:
The patent merges the control terminal formation into the vertical stack of semiconductor regions. The control terminal (second conductivity type) is integrated between the two conduction terminals (first conductivity type) in the vertical arrangement, combining multiple functions into a compact structure that eliminates the need for separate spacer structures
2Productivity
If more memory cells are formed in a single well, then memory capacity increases, but series resistance becomes too high
Solution Approach 1:
By stacking transistor regions vertically rather than arranging them laterally in the well plane, the patent enables higher density memory arrays. Multiple memory cells can be formed in a single well with improved current paths, increasing memory capacity without proportionally increasing series resistance
3Reliability
If spacers are added to prevent short-circuit during silicidation, then electrical isolation is improved, but memory cell size increases
Solution Approach 1:
The vertical arrangement of terminals eliminates the need for lateral spacer structures. Electrical isolation is achieved through the vertical stacking geometry and associated dielectric structures rather than lateral spacers, reducing memory cell footprint while maintaining electrical performance
Solution Approach 2:
The patent extracts the spacer component from the transistor structure entirely. The vertical bipolar transistor design achieves electrical isolation and prevents short-circuits through its inherent vertical geometry and dielectric layering, making the spacer structure unnecessary and thereby reducing memory cell size
Data Source
AI summary
The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.