Semiconductor Sidewall Mask Width Variation via Layered Etching
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Solution Overview
Problem
The sidewall mask process in semiconductor manufacturing is limited to forming patterns of a single width, preventing the simultaneous formation of patterns with different widths, which is a constraint in miniaturizing semiconductor devices like MRAM, ReRAM, and NAND flash memories where varying line widths are necessary to minimize chip area and prevent parasitic capacitance and voltage drop.
Innovation Solution
A method involving the formation of a covering material with stacked layers on semiconductor cores, where selective removal of layers allows for the creation of sidewall masks with varying widths, enabling the etching of patterns with different widths in parallel, thereby overcoming the limitations of traditional sidewall mask processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a traditional sidewall mask process is used, then patterns with consistent width can be formed, but patterns with different widths cannot be formed in parallel
Solution Approach 1:
The covering material is divided into multiple layers (first layer and second layer) with different etching rates. By selectively removing portions of specific layers, sidewall masks with different widths can be formed on different cores, enabling parallel processing of patterns with varying widths while maintaining process consistency
Solution Approach 2:
Different regions of the covering material are designed with different properties (different layers with different etching rates). The second layer is selectively removed from certain cores while retained on others, creating locally optimized sidewall mask widths tailored to specific pattern requirements without affecting the entire structure
2Manufacturing precision
If photolithography size is reduced to form smaller patterns, then miniaturization is achieved, but variations in width of processed patterns arise
Solution Approach 1:
The sidewall mask formed from the multi-layer covering material serves as an intermediary structure that defines the final pattern width. By controlling the thickness and selective removal of covering material layers, precise pattern widths can be achieved independent of photolithography limitations, eliminating width variations that occur with direct photolithographic scaling
Data Source
AI summary
According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.