2N Bi-polar Decoder Circuitry for Memory Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices utilizing 1P1N bi-polar decoders for resistance variable memory cells exhibit high power consumption due to changes in gate biases during polarity transitions, which is inefficient for selection and de-selection signals.
Innovation Solution
The use of 2N bi-polar decoders comprising two n-type transistors instead of one p-type and one n-type transistor, which maintains constant gate biases for unselected transistors during polarity transitions, reducing power consumption by providing eight configuration modes with reduced voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If 1P1N bi-polar decoders are used for resistance variable memory cells, then selection and de-selection signals can be generated, but power consumption increases due to gate bias changes during polarity transitions
Solution Approach 1:
The patent changes the transistor configuration parameter from 1P1N to 2N bi-polar decoder structure. This parameter change results in constant gate biases for unselected transistors during polarity transitions, eliminating the power consumption issue while maintaining selection and de-selection signal generation capability.
2Adaptability or versatility
If 1P1N bi-polar decoders are used, then decoder functionality is achieved, but voltage variations increase during polarity transitions
Solution Approach 1:
The patent modifies the decoder structure parameter from 1P1N to 2N configuration. This change ensures that gate biases remain constant for unselected transistors during polarity transitions, providing stable voltage composition while maintaining full decoder functionality for address decoding and signal generation.
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.