Digital Storage TRIZ Cases

A semiconductor memory data block selectively loads write data onto a global input output bus using a control signal to match actual burst length requirements.

Elevating the ground power supply signal weakens cross-coupled inverters during memory clearing operations.

A TCAM error detection method uses a parallel RAM copy with checksums to verify data integrity during read operations.

Calibration circuit samples pulse indicating signals using delayed enablement settings to adjust data strobe timing.

Back control gates modulate threshold voltage in series transistors, reducing area and power consumption while maintaining logic functionality.

Segmenting bit lines into local and global sections with dedicated sense amplifiers lowers parasitic resistance to improve integration density.

A memory driving circuit uses selective switching of a capacitive energy storage unit to adjust current amplitude and change rate.

A magnetic memory element uses a polarizing layer to deterministically switch storage magnetization via spin orbit torque.

Differentiated metal widths and parallel inactive lines reduce RC delay in high-density multibank memory arrays.

A pseudo-dual-port SRAM design segments bit line and sense amplifier precharging into independent circuits to accelerate memory operations.

Sense circuitry measures source line currents at incremental voltages to determine threshold voltage distributions in memory arrays.

A semiconductor storage device control circuit executes cancel and verify operations to manage memory cell states.

Cascode transistors buffer phase change memory resistance variations, expanding the read window while bank generators reduce output resistance.

Wrapping a FinFET gate around the channel reduces leakage current while maintaining high integration density in scaled SRAM cells.

A common source line compensation circuit supplies write currents to balance electrical conductivity in semiconductor memory arrays.

Vertical channel structure with body gate layer and charge storage reduces manufacturing complexity for high integration density.

A semiconductor device uses a latch circuit to store row addresses for smart refresh operations.

A hierarchical magnetic memory system uses segmented array tiles and global circuitry to control read and write operations efficiently.

A memory integrated circuit embeds a logic component to execute tasks directly on stored data within the array.

Removing metal liners from ReRAM stacks prevents spacer damage during via etching and improves resistance control.

An amorphous spin-orbit torque wiring reduces reversal current density, enabling magnetic memory data writing with minimal electric current.

Sequential voltage pulses transition a resistive memory cell state, reducing integral energy and improving reliability.

An internal voltage generation circuit uses an enable control circuit to limit activation timing and a start-up control circuit to manage reset operations.

A row-hammer control circuit manages first and second queues to select target refresh addresses based on access counting data.

A 2N bi-polar decoder circuit maintains constant gate biases during polarity transitions to reduce power consumption.

A memristor neuron circuit generates pulse trains via oscillation frequency thresholds to accelerate artificial neural network processing.

A command-address buffer chip filters refresh commands to reduce memory power consumption.

Applying high-frequency voltage pulses to restore remnant polarization in fatigued ferroelectric memory cells.

Sharing transistors between word line drivers reduces peripheral circuitry area while maintaining independent control signals.

A semiconductor memory internal voltage generating circuit adjusts back bias voltage levels dynamically.

A memory system with multiple detection circuits monitors access frequencies to enable targeted refresh operations.

Segmenting content-addressable memory into blocks reduces power consumption and heat generation by limiting active search entries during lookup operations.

Final column enable signal generator synchronizes row and column signals to eliminate data read errors from latency variations.

A sense amplifier uses a control module to configure current mirror structures for pre-amplifying bit line voltages.

A latch design uses delayed clock signals to maintain data storage node states against radiation disturbances.

A digital voltage boost circuit injects constant current pulses into memory bit lines to maintain stable bias levels during high frequency operation.

Segmenting the read path prevents magnetization switching during state detection while maintaining measurement precision.

A magnetic storage device uses a magnetoresistive effect element with hierarchical coercivity layers to generate stable reference currents.

A control circuit manages memory refresh times and address signals based on area setting data.

A semiconductor device stores bank addresses in a register to perform read and write operations using a single address signal.

A memory system selects low or high frequency oscillators to obtain delay values for tracking operations.

A magnetoresistive structure uses two dielectric layers and an encapsulation material on sidewalls to protect tunnel barriers during manufacturing.

Reference elements compare discharge currents to read resistive states, eliminating in situ selection circuitry and reducing cell physical dimensions.

Applying asymmetrical emphasis to a memory data bus driver compensates for capacitive and inductive load impedances that distort high-frequency signals.

A data alignment device buffers strobe signals and latches input data to ensure precise internal timing margins.

Applies segmented sensing voltages to distinguish memory states and reduce threshold distribution overlap.

A multi-bit memory cell uses a spin-orbit coupling layer to control critical currents across sequentially arranged magnetic tunnel junctions.

A signal processing circuit uses two switching devices to control a resistive random access memory.