Semiconductor Memory Data Block Selective Loading

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Solution Overview

Problem

Conventional semiconductor memory devices experience increased power consumption and noise due to unnecessary charging and discharging of the Global Input/Output (GIO) bus, as they write data in bursts longer than required, causing coupling issues on signal lines.

Innovation Solution

A circuit and method that selectively load data of a predetermined burst length or half of that length on the global bus, using a data block to control the loading operation, with a control signal generator, data input unit, data aligning unit, and global input/output transmitting unit, allowing the memory bank to write data efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If data is loaded in full burst length on the GIO bus, then data writing capability is maintained, but power consumption increases due to unnecessary charging and discharging

Engineering Contradiction:
Improvepower consumptionVSAvoiddata writing capability
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent applies partial action by loading only the necessary portion of data (e.g., 4 bytes) on the GIO bus instead of the full burst length (e.g., 8 bytes). The data block selectively loads data based on the actual burst length required, avoiding unnecessary charging and discharging of the GIO bus, thereby reducing power consumption while maintaining adequate data writing capability.

Inventive Principle:
Principle #16Partial or excessive action

2Object-affected harmful factors

If data is loaded in full burst length on the GIO bus, then data writing capability is maintained, but coupling noise increases on adjacent signal lines

Engineering Contradiction:
Improvecoupling noiseVSAvoiddata writing capability
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent reduces coupling noise by performing partial data loading on the GIO bus. By loading only the required data amount (e.g., 4 bytes instead of 8 bytes), the duration and extent of GIO bus activation is reduced, thereby minimizing coupling effects on adjacent signal lines while preserving necessary data writing functionality.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If the data block loads data according to burst length 8, then data writing is simplified, but unnecessary data is loaded increasing power consumption

Engineering Contradiction:
Improvedata writing operationVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent introduces dynamic adaptability by enabling the data block to selectively load data based on actual burst length requirements (e.g., choosing between 4 bytes or 8 bytes). This dynamic operation allows the system to adjust data loading behavior to match actual needs, avoiding unnecessary power consumption while maintaining ease of operation through automated selection based on write command parameters.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8031554B2Circuit and method for controlling loading of write data in semiconductor memory device
Publication Date: 2011.10.04 SK HYNIX INC
  • US8031554B2 patent drawing
  • US8031554B2 patent drawing
  • US8031554B2 patent drawing

AI summary

A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.