Ferroelectric Memory Count Detection Circuitry for Imprint Suppression
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Solution Overview
Problem
Ferroelectric memories face issues with imprint, leading to reduced polarization over time, which affects their functionality, and existing solutions increase circuit size, access time, and power consumption due to the need for timers and frequent access to all memory cells.
Innovation Solution
A memory system with multiple detection circuits to monitor access frequencies, allowing for targeted refresh operations to prevent imprint and disturbance, reducing the need for extensive circuitry and power consumption by only accessing memory cells when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a timer is provided to measure time for preventing imprint, then imprint can be suppressed, but circuit size increases
Solution Approach 1:
The patent extracts the time measurement function from a dedicated timer circuit and implements it using the existing count detection circuits that already measure access frequencies. The first count detection circuit measures total access frequency, while the second count detection circuit measures access frequency per memory cell block, allowing derivation of non-access time without requiring a separate timer circuit.
Solution Approach 2:
The count detection circuits are designed to serve multiple functions: they detect access frequencies for disturbance prevention and simultaneously provide the basis for imprint suppression by measuring non-access time. This multi-functionality eliminates the need for dedicated timer circuits while maintaining imprint suppression capability.
2Reliability
If access is performed to all memory cells each prescribed time, then imprint is suppressed, but power consumption increases
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively on memory cell blocks that require it. The second count detection circuit identifies which specific memory cell blocks have not been accessed for the prescribed time, and refresh operations are performed only on those blocks rather than all memory cells, thereby reducing power consumption while maintaining imprint suppression.
Solution Approach 2:
Instead of performing full refresh operations on all memory cells, the patent applies partial action by refreshing only the memory cell blocks that have not been accessed for the prescribed time. This partial refresh approach is sufficient to prevent imprint on affected blocks while avoiding unnecessary power consumption from refreshing blocks that were recently accessed.
3Reliability
If access is performed to all memory cells each prescribed time, then imprint is suppressed, but access period is shortened
Solution Approach 1:
The patent improves productivity by applying local quality to the refresh operation. Instead of periodically accessing all memory cells which interrupts the original access sequence, the system selectively refreshes only those memory cell blocks identified by the second count detection circuit as having non-access time exceeding the prescribed threshold. This minimizes interference with the original access period.
Solution Approach 2:
The patent uses partial action by performing refresh operations only on the subset of memory cell blocks that require it, rather than all blocks. This reduces the total time required for refresh operations and minimizes the impact on the original access period, thereby maintaining higher productivity.
Data Source
AI summary
A memory capable of suppressing increase in circuit size, reduction in a period for an original access and increase in power consumption while suppressing an imprint can be obtained. The memory includes a first count detection circuit for detecting an access frequency with respect to memory cells, a second count detection circuit for detecting an access frequency of each of memory cell blocks and a third count detection circuit detecting a no-access frequency resulting in an imprint.