FinFET SRAM Cell Leakage Reduction via 3D Gate Control
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Solution Overview
Problem
The rapid reduction in feature size of SRAM cells leads to increased leakage current, which is a challenge in the development of smaller electronic devices, as existing technologies struggle to effectively manage this issue.
Innovation Solution
The implementation of FinFETs (fin field effect transistors) in SRAM cells, which feature a gate structure that wraps around the active region on three sides, enhancing control over the channel and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but leakage current increases
Solution Approach 1:
The patent transitions from planar transistors to FinFETs, moving the active region from a two-dimensional plane to a three-dimensional fin structure that protrudes vertically from the substrate. This dimensional change allows the gate to wrap around three sides of the channel, providing stronger electrostatic control and reducing leakage current while maintaining small footprint for high integration density
Solution Approach 2:
The patent changes the physical and geometric parameters of the transistor structure by creating a vertical fin structure with specific dimensions (fin height, width, and depth). This parameter change enables the gate to control the channel more effectively, reducing off-state leakage current while preserving the compact form factor needed for high integration density
2Loss of energy
If FinFETs are used to reduce leakage current, then leakage current is reduced, but device structure becomes more complex
Solution Approach 1:
The patent employs a three-dimensional FinFET structure where the active region protrudes vertically from the substrate and the gate wraps around three sides. This dimensional approach reduces leakage current through improved electrostatic control while the fin geometry itself simplifies the overall device architecture compared to alternative approaches
Data Source
AI summary
A memory cell comprises a first word line in a first interconnect layer, a first VSS line, a first bit line, a power source line, a second bit line and a second VSS line formed a second interconnect layer, a second word line in a third interconnect layer. The memory cell further comprises a word line strap structure formed between the power source line and the second bit line, wherein the word line strap structure couples the first word line and the second word line.