Memristor Neuron Circuit for ANN Area Reduction
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Solution Overview
Problem
Existing artificial neural network (ANN) technologies face challenges in reducing the area and energy consumption of peripheral I/O circuits, which are essential for supporting ANN computing, as they often require additional reset circuits and capacitors, compromising their advantages.
Innovation Solution
A neuron circuit design incorporating a memristor and an integrator or current-voltage converter, which generates a pulse train with oscillation frequency when an applied voltage exceeds a predetermined threshold, allowing for efficient signal transmission between layers without the need for additional reset circuits or capacitors, utilizing memristor technology like spin-transfer torque magnetoresistive random access memory (STT-MRAM) for compactness and high-density neural network implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex digital-to-analog converter/analog-to-digital converter (DAC/ADC) circuits are used to realize I&F neurons, then the neuron circuit can perform integrate-and-fire functionality, but the area and energy consumption increase significantly
Solution Approach 1:
The patent replaces complex electronic DAC/ADC circuits with a memristor-based system that uses resistance switching to achieve integrate-and-fire functionality. The memristor's resistance changes in response to voltage thresholds, eliminating the need for traditional converter circuits and significantly reducing area.
Solution Approach 2:
The patent utilizes the resistance parameter of the memristor to encode neural signals. By changing the resistance state based on voltage thresholds, the system achieves neuron functionality without requiring complex circuitry, thus reducing the overall circuit area.
2Reliability
If additional reset circuits and capacitors are added to memristor-based neuron circuits, then the neuron circuit can maintain stable operation, but the area and energy consumption increase
Solution Approach 1:
The memristor-based neuron circuit is designed to be self-resetting through its inherent resistance switching characteristics. The circuit automatically returns to its initial state after firing without requiring external reset circuits, achieving stability while minimizing area.
Solution Approach 2:
The patent extracts and eliminates the need for separate reset circuits and capacitors by leveraging the memristor's intrinsic properties. The memristor's resistance switching behavior naturally provides the reset function, removing unnecessary components and reducing circuit area.
3Productivity
If traditional crossbar architecture is used for ANN computing, then matrix multiplication can be accelerated, but the von Neumann bottleneck of inefficient data transfer remains
Solution Approach 1:
The patent merges the computing and storage functions into a unified memristor crossbar architecture. The synapse array of memristors performs both weight storage and multiplication operations simultaneously, eliminating the separation between memory and computation that causes the von Neumann bottleneck.
Solution Approach 2:
The patent replaces traditional von Neumann architecture with an in-memory computing approach using memristors. The computational operations are performed directly within the memory array, eliminating inefficient data transfer between separate memory and processing units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a high-density artificial neural network chip with reduced area and energy consumption, enabling efficient deep-learning acceleration through compact all-spin artificial neural networks and stochastic binary synapses, leveraging the Back Hopping oscillation mechanism in magnetoresistive memory for current integration and voltage spike generation.
Implementation Method 1
The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold
Implementation Method 2
The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times
Data Source
AI summary
A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.