3D Memory Vertical Channel Structure Integration
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Solution Overview
Problem
As the degree of integration of memory devices increases, manufacturing processes for memory devices with vertical transistor structures become increasingly difficult due to the complexity of forming cell contact layers and charge storage structures at the bottom portion of channel holes, limiting the vertical height and integration of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a channel structure with a body gate layer and charge storage structure extending vertically, surrounded by a channel layer, with a gate insulating layer between gate electrodes and the channel structure, allowing for independent voltage application to the gate electrode and body gate layer for data storage, reducing the need for complex processes like selective epitaxial growth and minimizing disturbance between word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the degree of integration of memory devices increases, then the vertical height of the device increases, but the manufacturing process complexity increases significantly
Solution Approach 1:
The device is divided into multiple functional layers including channel structures, charge storage structures, blocking dielectric layers, and tunneling dielectric layers stacked vertically. Each layer performs a specific function, allowing complex functionality to be achieved through modular layering rather than monolithic structures, thereby managing manufacturing complexity while increasing vertical integration.
Solution Approach 2:
The patent transitions from planar 2D memory structures to vertical 3D structures by stacking channel holes and gate electrodes in the vertical direction (Z-axis). This dimensional change enables increased storage capacity and device height without proportionally increasing manufacturing process complexity, as the vertical stacking follows a repetitive pattern that can be manufactured using standard semiconductor fabrication techniques.
2Quantity of substance
If the degree of integration increases, then more gate electrode layers are stacked vertically, but manufacturing difficulty increases
Solution Approach 1:
Charge storage structures are formed in the channel holes before the channel layer is deposited. This preliminary formation of the charge storage structure simplifies subsequent manufacturing steps by establishing the core functional element first, around which other layers (channel layer, blocking dielectric, tunneling dielectric) can be systematically added without requiring complex selective epitaxial growth processes.
Solution Approach 2:
Instead of forming the channel layer first and then adding charge storage structures (which would require complex selective epitaxial growth), the patent inverts the sequence by forming charge storage structures first in the channel holes, then depositing the channel layer around them. This inversion simplifies the manufacturing process by using conformal deposition techniques rather than complex selective growth.
3Quantity of substance
If vertical transistor structures are used, then integration density increases, but processes for forming cell contact layers and charge storage structures at the bottom of channel holes become increasingly difficult
Solution Approach 1:
The charge storage structures are formed in the channel holes before the channel layer is deposited. This preliminary action ensures that the charge storage structures are precisely positioned at the required locations without requiring complex subsequent alignment steps, thereby maintaining manufacturing precision while achieving high integration density.
Solution Approach 2:
The blocking dielectric layer serves as an intermediary between the charge storage structure and the channel layer. This intermediary layer simplifies the formation process by providing a defined interface that eliminates the need for complex selective epitaxial growth to form cell contact layers, as the blocking dielectric can be deposited conformally over the charge storage structures.
4Quantity of substance
If more gate electrode layers are stacked, then storage capacity increases, but disturbance between word lines increases
Solution Approach 1:
The tunneling dielectric layer is selectively formed only in specific regions where charge storage is required, rather than uniformly across all gate electrodes. This local quality approach allows charge to be stored only in selected memory cells, reducing electrical disturbance and interference between adjacent word lines while maintaining high storage capacity through selective activation of memory cells.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.