Self-Aligned ReRAM Integration Without Metal Liners
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Solution Overview
Problem
Current methods for integrating Resistive Random-Access Memory (ReRAM) into lower BEOL levels face challenges such as damage to conventional spacers during Via open processes and weak spots in TiN wet etching, particularly due to larger Cu Via dimensions compared to ReRAM stack pillars, which affect the formation of crossbar ReRAM structures.
Innovation Solution
A method for concurrently forming a logic circuit and a crossbar ReRAM array on the same device, where the ReRAM stack is self-aligned with metal layers, and no metal liner is formed on the sidewalls of the ReRAM stack, allowing for better resistance control and avoiding damage during patterning and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional spacers are used during Via open processes, then the ReRAM stack can be formed, but the spacers are damaged due to larger Cu Via dimensions
Solution Approach 1:
The patent removes the metal liner layer from the ReRAM stack structure, extracting the problematic component that caused damage during Via open processes. This eliminates the need for protective spacers and their associated damage issues, allowing direct formation of Cu Vias through the dielectric layer to contact the ReRAM stack.
Solution Approach 2:
Instead of protecting the ReRAM stack with metal liners and spacers during Via formation, the patent inverts the approach by forming Vias first through the dielectric layer, then forming the ReRAM stack in the same process sequence. This reversal eliminates the need for protective structures that get damaged during Via opening.
2Strength
If metal liner is formed on sidewalls of ReRAM stack, then structural support is provided, but weak spots are created in TiN wet etching
Solution Approach 1:
The patent extracts the metal liner layer from the ReRAM stack structure, removing the source of weak spots that caused non-uniform TiN wet etching. The ReRAM stack is formed without sidewall metal liners, eliminating the differential etching rates between metal liner and TiN materials.
3Quantity of substance
If ReRAM is integrated into lower BEOL levels, then high density is achieved, but damage to underlying layers occurs during patterning and etching
Solution Approach 1:
The patent performs preliminary actions by forming the ReRAM stack and interconnect structure in the lower BEOL levels before forming the Cu interconnect layers. This sequence allows the ReRAM structure to be established and protected before subsequent high-energy patterning and etching processes occur in upper layers.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the ReRAM stack and the Cu interconnect layers. This dielectric mediator protects the underlying ReRAM structure during subsequent patterning and etching processes, preventing direct damage while allowing electrical connection through formed Vias.
Data Source
AI summary
A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.