Row-Hammer Control Circuit with Dual Queues for Target Refresh
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Solution Overview
Problem
Existing memory systems face challenges in effectively mitigating the row-hammer phenomenon, which causes data loss due to excessive activations of specific word lines, leading to inefficient data retention and potential system failures.
Innovation Solution
A memory device with a row-hammer control circuit that manages first and second queues based on access counting values, selectively performing target refresh operations on rows with high activation counts to prevent data loss and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a target refresh operation is performed on rows with high activation counts to mitigate row-hammer phenomenon, then data retention and system reliability are improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively on specific rows that exhibit high activation counts or are adjacent to such rows, rather than uniformly refreshing all rows. The row-hammer control circuit identifies target rows based on activation counting and executes refresh operations only on those specific rows, thereby concentrating power consumption where it is most needed to mitigate row-hammer effects while preserving data integrity in vulnerable regions.
2Measurement precision
If activation counting and queue management are implemented to identify target rows, then row-hammer mitigation precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the row management function into distinct components: an activation counting unit that tracks row access frequencies, a row-hammer control circuit that processes the counting data, and a queue structure that manages target row addresses. This segmentation allows each component to perform its specific function efficiently, with the counting unit focusing on measurement, the control circuit on decision-making, and the queue on organization, thereby achieving precise row identification while distributing complexity across modular functional blocks.
Solution Approach 2:
The patent introduces an intermediary queue structure that stores target row addresses between the counting unit and the refresh execution mechanism. This queue acts as a buffer and organizer, allowing the control circuit to process counting data and generate target row addresses without directly interfacing with the refresh operation hardware, thereby simplifying the control logic while maintaining precise row identification capabilities.
Data Source
AI summary
A memory device includes a memory cell region including a plurality of rows; a row-hammer control circuit including first and second queues, and configured to: read counting data from a row indicated by a row address according to an active command, store the row address in the first queue according to a comparison result of the counting data and a first set value, store the row address in the second queue according to a comparison result of the counting data and a second set value, and select, as a row-hammer address according to a refresh management command or a target refresh command, one of the row addresses stored in the first queue and the second queue; and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command.