Latch Design for Radiation Hardness via Delayed Clock Signals
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Solution Overview
Problem
Programmable logic devices, such as CPLDs and FPGAs, are vulnerable to unintentional state changes in data storage nodes due to radiation effects like single-event upsets (SEUs) and single-event transients (SETS), which can lead to data loss and incorrect system operation, and existing solutions like triple modular redundancy and dual interlocked storage cells do not effectively prevent SETs.
Innovation Solution
A latch design that incorporates a delay circuit to generate delayed clock and data signals, allowing the latch to distinguish between valid and invalid signals based on pulse width, thereby preventing glitches caused by SEUs and SETs from changing the stored data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy is used to prevent SEUs, then data reliability is improved, but circuit complexity and cost increase significantly
Solution Approach 1:
The latch is segmented into multiple data storage nodes (first, second, and third nodes) with separate clocking paths. Each node is controlled by clock signals with different delay characteristics, allowing independent validation of data transitions. This segmentation enables the circuit to detect and reject SET-induced glitches without requiring full triple modular redundancy of the entire latch structure.
2Reliability
If dual interlocked storage cell is used to prevent SEUs, then upset hardness is improved, but protection against SETs is not achieved
Solution Approach 1:
The invention introduces dynamic clock signal delay adjustment to adapt to different glitch conditions. By varying the delay amount in the clock path, the latch can dynamically respond to different pulse widths caused by SET events. This dynamic adaptation allows the same dual interlocked structure to provide both SEU and SET protection by adjusting timing parameters rather than requiring separate static protection circuits.
3Reliability
If delay circuit is added to generate delayed clock signal, then SET protection is improved, but device complexity increases
Solution Approach 1:
The delay circuit performs preliminary action by pre-delaying the clock signal before it reaches the data storage nodes. This preliminary delay creates a time window that allows SET-induced glitches to be filtered out before they can affect the latched data. By preparing the clock signal in advance with the appropriate delay, the circuit proactively prevents SET effects without requiring complex real-time detection and correction mechanisms.
Data Source
AI summary
A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.