Memory Control Circuit for Defect Area Management
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Solution Overview
Problem
Integrated memory devices face defects that render the entire memory device unusable, necessitating the division of memory cells into usable and non-usable areas, which complicates operational efficiency and requires different operation characteristics for each scenario.
Innovation Solution
A control circuit that includes a refresh time control circuit, an address control circuit, and a fragment control circuit, which sets refresh times and addresses based on area setting signals to optimize memory usage, allowing for flexible operation characteristics and efficient use of memory areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire memory cell is divided into multiple areas to cope with defects, then the usability of the memory device is improved, but the operational complexity increases due to different operation characteristics required for each scenario
Solution Approach 1:
The control circuit is designed to perform multiple functions: it can operate in full-memory mode when no defects are present and in partial-memory mode when defects are detected. The same control circuit handles both scenarios by responding to different area setting signals, eliminating the need for separate control circuits for each mode and reducing overall system complexity while maintaining reliability
2Productivity
If different operation characteristics are set for full memory usage and partial memory usage, then the operational efficiency is improved, but the control circuit complexity increases
Solution Approach 1:
The control circuit dynamically adjusts its operation based on the area setting signal. When the signal indicates full memory usage, the control circuit operates with characteristics optimized for complete memory access. When the signal indicates partial memory usage due to defects, the control circuit automatically switches to different operation characteristics that optimize performance for the available memory areas, achieving high operational efficiency without requiring multiple static control circuits
Solution Approach 2:
The invention changes operational parameters (such as refresh time, address mapping, and bank selection) based on the area setting signal. By dynamically adjusting these parameters according to the actual memory availability, the control circuit achieves optimal operational efficiency for both full and partial memory usage scenarios while maintaining a single unified control structure
3Reliability
If only defect-free areas are used, then the memory device yield is improved, but the available memory capacity is reduced
Solution Approach 1:
The invention extracts and isolates the defective areas from the memory device, allowing them to be excluded from operation. The area setting signal identifies which memory areas are defective and extracts them from the usable memory space. This extraction approach maximizes the use of defect-free areas while clearly delimiting the boundaries of usable memory, thereby improving yield without unnecessarily reducing capacity
Data Source
AI summary
A control circuit may include a refresh time control circuit configured for controlling a refresh time on the basis of an area setting signal for setting a usage area of a memory. The control circuit may include an address control circuit configured for fixing at least one bit included in an external address on the basis of the area setting signal and an area mode signal and provide an internal address.