Hierarchical Bit Line Structure for DRAM Integration Density
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Solution Overview
Problem
Existing semiconductor memory devices face performance issues due to increased parasitic capacitance and resistance in large DRAMs, particularly when using hierarchical bit line structures, which hinder the integration and efficiency of memory cell arrays and require larger areas for sense amplifiers.
Innovation Solution
A semiconductor memory device with a hierarchical memory cell array configuration that uses single-ended sense amplifiers connected directly to local bit lines, reducing parasitic capacitance and resistance by shortening bit line lengths and employing a hierarchical structure with local and global bit lines, allowing for higher integration and faster access speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a hierarchical memory cell array with local bit lines is configured, then integration density is improved, but parasitic capacitance and resistance of bit lines increase
Solution Approach 1:
The bit line is divided into local bit lines and global bit lines. Local bit lines are shortened to reduce parasitic capacitance and resistance, while global bit lines handle the long-distance transmission. This segmentation allows high integration density without excessive parasitic effects.
Solution Approach 2:
Local sense amplifiers are introduced as intermediaries between memory cells and global sense amplifiers. These local sense amplifiers are connected directly to local bit lines to amplify signals before they are transmitted through global bit lines, compensating for signal degradation.
2Device complexity
If single-ended sense amplifiers are used instead of differential sense amplifiers, then circuit scale is reduced, but ability to amplify minute potential difference deteriorates
Solution Approach 1:
Local sense amplifiers serve as intermediaries that amplify the minute potential difference from local bit lines before the signal is transmitted to global bit lines. This allows single-ended amplifiers to achieve sufficient gain without requiring differential configurations.
Solution Approach 2:
The sense amplifier function is segmented into local and global levels. Local sense amplifiers handle the sensitive amplification task close to the memory cells, while global sense amplifiers handle the final output. This segmentation enables the use of simpler single-ended amplifiers at the local level.
3Device complexity
If sense amplifiers are connected to global bit lines instead of local bit lines, then circuit configuration is simplified, but operating performance deteriorates due to long bit line length
Solution Approach 1:
The sense amplifier system is segmented into local and global components. Local sense amplifiers are connected directly to local bit lines for fast signal amplification, while global sense amplifiers are connected to global bit lines for final output. This segmentation maintains both simplicity and high operating performance.
Data Source
AI summary
A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line.