Resistive Memory Cell Pulse Control for Stress Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently writing data due to high stress applied to memory cells during voltage transitions, leading to potential deterioration and reduced reliability.
Innovation Solution
A semiconductor memory device design that includes a memory cell with a resistance change film and a metal film, where a first pulse and a second pulse of different voltages are applied to transition the memory cell between high and low resistance states, reducing stress by increasing vacancy concentration and optimizing pulse widths and voltages to facilitate copper ion diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single high-voltage pulse is applied to transition the memory cell between resistance states, then the data writing speed is improved, but the stress applied to the memory cell increases leading to potential deterioration
Solution Approach 1:
The single high-voltage pulse is segmented into multiple pulses with different voltage levels. A first pulse with a first voltage level transitions the memory cell from high resistance to low resistance state, while a second pulse with a second voltage level (lower than the first) transitions it back. This segmentation reduces the stress on the memory cell compared to using a single high-voltage pulse, thereby improving reliability while maintaining data writing speed.
2Reliability
If the voltage and current applied to memory cells is reduced to decrease stress, then the reliability is improved, but the data writing efficiency decreases
Solution Approach 1:
The voltage and current parameters are optimized to specific levels that balance stress reduction with efficient data writing. The first pulse uses a first voltage level sufficient to transition the memory cell state efficiently, while the second pulse uses a lower second voltage level to reduce stress. This parameter optimization ensures that reliability is improved without significantly compromising data writing efficiency.
3Reliability
If the pulse width is increased to facilitate copper ion diffusion, then the resistance state transition is improved, but the time required for data writing increases
Solution Approach 1:
The data writing process uses periodic pulsing with two distinct voltage levels. The first pulse provides sufficient duration and voltage to facilitate copper ion diffusion and achieve reliable resistance state transition, while the second pulse with lower voltage maintains the transition without requiring extended time. This periodic action with varying voltage levels ensures reliable transitions without excessive data writing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the integral value of voltage and current applied to memory cells, reducing stress and improving data writing efficiency while maintaining reliability by lowering the barrier for copper ion diffusion through vacancies.
Implementation Method 1
the control circuit performs a first writing operation by applying a first pulse to the memory cell and applying a second pulse to the memory cell continuously after applying the first pulse... perform transition of a resistive state of the memory cell
Implementation Method 2
facilitate copper ion diffusion... lowering the barrier for copper ion diffusion through vacancies
Data Source
AI summary
According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell. The control circuit performs a first writing operation by applying a first pulse having a voltage of a first polarity to the memory cell and applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell continuously after applying the first pulse.