Common Source Line Compensation Circuit for Memory Noise Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining stable operation due to noise voltage induced in the common source line, which affects the reliability of data storage and retrieval, especially during concurrent write operations.
Innovation Solution
A semiconductor memory device is designed with a common source line compensation circuit that supplies compensation write currents to balance the current flow, using compensation cell units and a compensation mode selection circuit to manage data patterns and minimize noise, thereby stabilizing the common source line voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent write operations are performed to increase write bandwidth, then productivity is improved, but noise voltage in the common source line increases causing instability
Solution Approach 1:
The patent introduces a compensation circuit as an intermediary component that includes compensation transistors and compensation capacitors. This compensation circuit acts as a mediator between the common source line and the bit lines, actively counteracting noise voltage by generating compensating signals that cancel out the noise induced by concurrent write operations, thereby maintaining voltage stability while allowing high-speed concurrent writes
2Reliability
If multiple compensation circuits are added to reduce noise, then reliability is improved, but device complexity increases
Solution Approach 1:
The compensation circuit is segmented into multiple independent compensation units, each associated with specific bit lines. Each compensation unit contains compensation transistors and capacitors that can be independently controlled. This segmentation allows the system to apply compensation only where and when needed, rather than using a single complex global compensation mechanism, thereby reducing overall circuit complexity while maintaining effectiveness
Solution Approach 2:
The compensation circuit employs dynamic control mechanisms where compensation transistors are selectively activated based on the write operation pattern. The circuit dynamically adjusts the compensation level by controlling the switching states of compensation transistors, enabling the system to adapt to different write scenarios and minimize noise only when necessary, thus avoiding the need for permanently active complex compensation structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise in the common source line, enhancing the stability and reliability of data storage and retrieval operations, even during high-speed concurrent write operations, by balancing current flow and managing data patterns.
Implementation Method 1
the amount of current flowing in one direction or the other direction is determined according to the pattern of X8 and X16 data. As a result, the current is output from or input into the common source line and noise voltage induced to the common source line may be changed according to the data pattern based on the resistance value of the common source line
Data Source
AI summary
A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.