2N Memory Pre-Decoder Circuitry for Static Gate Biasing
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Solution Overview
Problem
Existing memory devices utilizing 1P1N bi-polar decoders for resistance variable memory cells exhibit significant power consumption due to changing gate biases during polarity transitions, which is inefficient and increases circuit complexity.
Innovation Solution
Implementing decoder circuitry with two n-type transistors (2N bi-polar decoders) to provide selection and de-selection signals, maintaining static gate biases during polarity transitions, thereby reducing power consumption and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If 1P1N bi-polar decoders are used for resistance variable memory cells, then selection and de-selection signals can be provided, but power consumption increases significantly due to changing gate biases during polarity transitions
Solution Approach 1:
The patent changes the transistor configuration from 1P1N (one p-type, one n-type) to 2N (two n-type) bi-polar decoders. This parameter change in the circuit topology allows both transistors to share the same gate bias voltage, eliminating the need to change gate biases during polarity transitions and thereby significantly reducing power consumption while maintaining decoder functionality
Solution Approach 2:
The 2N decoder configuration provides universal operation for both positive and negative resistance variable memory cell configurations. The same decoder circuit with static gate biases can selectively access memory cells regardless of polarity, making the circuit multi-functional and eliminating the need for separate decoder paths for different polarities
2Ease of operation
If 1P1N bi-polar decoders are used, then memory cell selection is achieved, but circuit complexity increases
Solution Approach 1:
Changing from 1P1N to 2N transistor configuration simplifies the circuit by allowing both transistors to operate with the same gate bias voltage. This parameter change reduces the number of different voltage rails needed and simplifies the biasing network, thereby reducing circuit complexity while maintaining full selection capability
3Adaptability or versatility
If gate biases change during polarity transitions in 1P1N decoders, then memory cell access is enabled, but power consumption increases
Solution Approach 1:
The patent changes the fundamental operating parameter of gate bias voltage from dynamic (changing during polarity transitions) to static (constant). The 2N decoder configuration allows both n-type transistors to operate with the same static gate bias voltage regardless of memory cell polarity, eliminating energy consumption associated with bias voltage switching while maintaining adaptability to different polarities
Data Source
AI summary
The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuity to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.