Digital Storage TRIZ Cases

Frontside and backside bit lines with location-based widths cut resistance and parasitic capacitance in memory arrays.

Adaptive data mapping and shift-based fetching cut redundant buffer accesses in multi-storage-row CIM, improving neural network throughput and energy use.

Shared read-write circuits let distributed MRAM arrays power down between accesses, cutting layout area and power use.

Stacked MTJ memory cells with local line drivers and spin Hall writing raise density while limiting access-time and power penalties.

A dual-oxide insertion layer within a three-region DRAM capacitor dielectric boosts capacitance while preserving low leakage and reliability.

Using two n-type transistors with static gate biases, this memory pre-decoder reduces polarity-transition power use and circuit complexity.

A current spike followed by a low-amplitude pulse resets phase-change memory faster while cutting energy dissipation in 3D crosspoint arrays.

A test mode control circuit detects metal line resistance defects through delayed word line signals and helps maintain stable signal transmission.

A vertically stacked resistive memory structure spaces variable resistance layers to lower program-erase bias and reduce inter-cell interference.

Selective dual-DFE training confirms ISI, then applies current-summer or Gm-control equalization to improve signal integrity with lower current.

A structured MgO-based nonmagnetic layer dissipates write heat in domain wall elements, preserving magnetization stability and data reliability.

Wavelength-division multidrop links let multiple memory buffer ICs share one waveguide, boosting DRAM bandwidth while cutting optical assembly complexity.

By averaging accumulation results in capacitor pairs inside a CIM array, this case cuts processor-memory transfer delays in neural network MAC operations.

Separate read and write control circuits shift memory reference voltage levels to speed reads and track write operating voltage more accurately.

Gradual input-voltage ramping cuts parasitic-capacitance disturbance in crossbar VMM operations, reducing unintended programming and compute errors.

A current compliance layer stabilizes low-resistance states by limiting surge current and heat, improving Hamming distance accuracy in memory.

Detects repaired row addresses and row hammer conditions to drive normal or redundancy word lines and protect adjacent-cell data reliability.

A heat barrier enables high-temperature annealing of polarizable memory cells, while a capacitive divider lowers write stress to improve retention.

Helper memory cells share access lines to boost seasoning current, lowering threshold voltage and improving reliable access in hot conditions.

A PMOS underdrive and negative gate bias keep SRAM word-line underdrive stable across process and temperature shifts, improving bitcell margin.

Adjacent bit lines are split across two ECC modules and opposite-side sense amplifiers to cut ECC area and complexity while improving error correction.

Stacked word lines and threshold-switching layers form bit line contacts that raise memory integration and capacity beyond planar layouts.

Reading MRAM cells during both charge and discharge phases cuts read energy by 40% while preserving accurate bit-state sensing.

Enable-gated power control cuts standby leak current in semiconductor memory processing circuits while preserving fast data processing.

NMOS pre-sensing compensates threshold voltage mismatch before main sensing, cutting DC through-current, pattern noise, and power use.

Collective writing across segmented magnetic domains cuts write energy per bit while shifting stored information through dedicated wiring.

A voltage-driven magnetoelectric layer helps MTJ arrays switch with lower power and less write disturb as memory cells scale.

A current mirror and word-line bias keep SRAM bit lines above the bit-flip threshold during multi-row in-memory compute reads.

Vertically stacked nanoribbon memory cells use wraparound hysteretic capacitors to raise density while reducing footprint and disturbance sensitivity.

Separate high and low CS pulse results on multiple DQ pins improve clock alignment and reduce misalignment in high-speed memory training.

Bank-select signals and a discharge transistor shrink multi-bank decoding circuits, cutting area and transistor count without hurting memory operation.

A strong-arm comparator cuts calibration delay in 3D NAND, enabling timely impedance matching to reduce signal reflection and errors.

WDM-encoded optical states and programmable ring resonators enable parallel CAM search with lower area and energy use.

Precomputed PVT look-up codes shorten ZQ calibration in memory chips while preserving ODT impedance matching across temperature and voltage changes.

Connecting blocks expand neuromorphic synapse arrays without signal level change, supporting pruning, dropout, and higher learning accuracy.

Vertical paraelectric and ferroelectric stacking adjusts capacitance without enlarging cell area and protects the ferroelectric film from plasma damage.

A resistive memory element in series with a switching path creates four distinct states, raising NVM bit density while preserving read distinction.

Tracking wiring delays memory control signals by word-line depth to synchronize modulation, protect read/write margins, and cut crowbar current.

A composite MTJ sidewall layer uses Poole-Frenkel conduction to shunt spike currents, reducing tunnel barrier damage and write errors in MRAM.

Placing sub peripheral circuits beneath each memory subarray cuts DRAM core area while preserving design margin and sensing performance.

Low-hydrogen dielectric isolation limits diffusion at the OS interface, stabilizing TFTs and improving non-volatile data retention.

A higher-capacitance second capacitor accumulates FTJ leakage charge at a transistor gate to widen the read window and speed memory-state detection.

A three-stage internal clock scheme cuts RC delay and toggle power in memory arrays, improving access time without added silicon area.

A 3D memory string with select transistors boosts integration while easing fabrication and enabling faster low-voltage read and write access.

Per-pin ODT tuning aligns DQ pin impedance and voltage levels to cut reflection, noise sensitivity, and signaling variation in memory I/O.

A 3D stack with orthogonal word and bit lines plus dual sub-word line drivers packs more memory cells into a smaller chip area.

Separate row and column pins with edge-timed command input cut memory command latency and improve bank interleave throughput.

A level shifter delays the word line edge across voltage domains to prevent early reads and improve memory noise margin.

Using CFET selection transistors, this memory circuit separates read and write paths to limit source degeneration and stabilize operating voltage.

XNOR and XOR are generated in one memory cycle to remove memory-compute bandwidth bottlenecks and cut BNN energy use.