Per-Pin ODT Calibration for Memory Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memories face issues with impedance mismatch and varying signaling characteristics among DQ pins, leading to performance degradation due to external noise and signal reflection, which existing impedance adjustment methods fail to adequately address.
Innovation Solution
A memory device with per-pin calibration circuits that adjust impedance and voltage levels for each signal pin, using ODT and ZQ calibration to ensure uniform signaling characteristics across all DQ pins, thereby reducing variations and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impedance adjustment (ZQ) calibration is performed using external resistance, then impedance mismatch is reduced, but per-pin signaling characteristic variations remain due to different DQ pin environments
Solution Approach 1:
The patent segments the impedance adjustment from a global approach to per-pin individual calibration. Each DQ pin receives its own calibration sequence where the per-pin calibration circuit compares the pin's signaling characteristics against reference pins and adjusts ODT resistance independently. This segmentation allows each pin to be optimized for its specific environmental conditions while maintaining overall system reliability.
Solution Approach 2:
The patent applies local quality by providing customized impedance adjustment for each DQ pin based on its unique signaling characteristics. The per-pin calibration circuit identifies which pins have deviating characteristics and applies targeted ODT resistance adjustments only to those pins, rather than uniformly adjusting all pins. This ensures each pin operates with optimal impedance matching for its specific circuit environment.
2Speed
If swing width of signal is reduced to minimize transmission time, then data capacity and speed are improved, but influence of external noise and signal reflection increases
Solution Approach 1:
The patent changes the impedance parameter (ODT resistance) for each DQ pin to compensate for the reduced swing width. By adjusting the ODT resistance value based on per-pin calibration results, the system maintains proper impedance matching even with lower signal swing widths, thereby reducing signal reflection and the impact of external noise while preserving high-speed operation.
3Manufacturing precision
If per-pin calibration is implemented, then signaling characteristic uniformity is improved, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent implements universality by designing a per-pin calibration circuit that can service multiple DQ pins through a shared reference structure. The calibration circuit uses a common reference pin or reference signal generation mechanism that multiple DQ pins can be compared against sequentially. This multi-functional approach reduces the overall complexity compared to having completely independent calibration circuits for each pin while still achieving per-pin optimization.
Data Source
AI summary
Provided are a memory device and a method for training per-pin operation parameters. A memory device includes a plurality of on-die termination (ODT) circuits, an impedance control (ZQ) calibration circuit configured to output a first code signal and a second code signal, and a per-pin calibration circuit. The per-pin calibration circuit may be configured to select one signal pin from among the plurality of signal pins, to compare a first input voltage level of the selected signal pin with a second input voltage level of each of the other ones of the plurality of signal pins, to generate a per-pin ODT code signal for each of the plurality of signal pins, to combine the per-pin ODT code signal with the first code signal or the second code signal, and to provide the combined per-pin ODT code signal to the respective ODT circuits.