3D Memory Cell Stack Layout With Dual Word Line Drivers
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Solution Overview
Problem
Conventional semiconductor memory devices with two-dimensional memory cells are limited in integration capacity due to the area occupied by each unit cell, hindering the development of higher-capacity devices required for miniaturized and multifunctional electronic products.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack region containing word lines and bit lines arranged in orthogonal directions, featuring sub-word line drivers connected through word line contacts to increase the number of memory cells per horizontal direction, thereby enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory cells are used, then the device structure is simple, but the degree of integration is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional structure by stacking multiple memory cell layers vertically. Word lines are arranged in multiple layers at different heights, and bit lines extend vertically to connect to memory cells across multiple layers, enabling increased integration capacity while maintaining manageable structural complexity through systematic layering
2Quantity of substance
If more memory cells are packed in horizontal direction, then the degree of integration increases, but the area occupied by each unit cell increases
Solution Approach 1:
Instead of increasing the horizontal area of each memory cell to pack more cells, the patent utilizes the vertical dimension by stacking multiple memory cell layers. This allows a large number of memory cells to be packed within a compact horizontal footprint, as cells are distributed across multiple vertical layers rather than spread out horizontally
3Quantity of substance
If three-dimensional structure is implemented, then the degree of integration increases, but the device complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers, each containing word lines and memory cells. Word lines are segmented into different layers (first plurality at first height, second plurality at second height), and bit lines are segmented into vertical interconnect structures. This segmentation allows the complex 3D structure to be managed as a series of simpler, repeatable layers
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing word lines and memory cells that are nested within the overall 3D architecture. Bit lines nest vertically through multiple layers to connect to memory cells across different heights, creating a compact nested arrangement that increases integration while controlling complexity
Data Source
AI summary
Provided is a semiconductor memory device including a substrate including a stack region, the stack region including a first step region and a second step region being at both ends of the stack region in a first horizontal direction, a plurality of word lines each extending in the first horizontal direction in the stack region, a plurality of bit lines extending in the vertical direction and spaced apart from each other in the first horizontal direction in the stack region, a plurality of memory cells between the plurality of word lines and the plurality of bit lines, a first word line contact and a second word line contact connected to each of the plurality of word lines, and a first sub-word line driver and a second sub-word line driver connected to the first word line contact and the second word line contact, respectively.