CFET Memory Circuit for Stable Read-Write Voltage Control
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Solution Overview
Problem
As semiconductor integrated circuits become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, particularly in memory devices like RRAM, MRAM, and PCRAM, leading to issues with reliability and power performance.
Innovation Solution
The use of complementary field-effect transistors (CFETs) in memory circuits, where different transistors perform write operations for different logical values, simplifying peripheral circuitry and reducing source degeneration, thereby improving reliability and power performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory circuits are used with increasing IC complexity and smaller dimensions, then device integration is achieved, but resistance of conductive lines increases affecting operating voltages and performance
Solution Approach 1:
The patent changes the voltage parameter by using a selection circuit that applies different voltages to different bit lines. The first bit line receives a first voltage while the second bit line receives a second voltage, allowing the memory circuit to operate correctly despite increased resistance from smaller dimensions and higher integration.
2Productivity
If conventional memory circuits are used with increasing IC complexity, then device integration is achieved, but power performance deteriorates
Solution Approach 1:
The patent applies local quality by providing different voltages to different bit lines based on their specific requirements. The selection circuit identifies which bit line needs access and applies the appropriate voltage only to that specific line, rather than uniformly increasing voltage across all lines, thereby improving power performance while maintaining integration.
3Ease of operation
If selection circuit applies voltage to both bit lines, then memory cell access is enabled, but source degeneration occurs reducing reliability
Solution Approach 1:
The patent inverts the conventional approach by applying voltage differentially: the first bit line receives a first voltage while the second bit line receives a second voltage (ground or different level). This inversion prevents source degeneration that would occur if both lines received the same voltage, while still enabling proper memory cell access through the selection circuit.
Data Source
AI summary
A memory circuit includes a bit line driver circuit, a first bit line, a selection circuit, a first word line, a first source line, and a memory cell. The selection circuit includes a first transistor on a first level of a substrate; and a second transistor on a second level of the substrate below the first level. The first transistor and the second transistor are part of a complementary field-effect transistor (CFET). The first transistor is configured to perform a write operation of the memory cell in response to the memory cell being configured to store a first logical value. The second transistor is configured to perform a read operation of the memory cell, and the write operation of the memory cell in response to the memory cell being configured to store a second logical value different from the first logical value.