Stacked MTJ Memory Cell Layout for High-Capacity Low-Power Access
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Solution Overview
Problem
Existing memory devices face challenges in achieving high storage capacity with low power consumption, particularly in applications like cache memory and main memory, where fast access times and reduced power consumption are required.
Innovation Solution
A memory device structure is proposed with layers including a circuit and memory cells, utilizing transistors with metal oxide in the channel formation region and incorporating a conductor that causes the spin Hall effect, along with MTJ elements featuring a free layer and a fixed layer, to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity is improved, but access time and power consumption characteristics deteriorate
Solution Approach 1:
The memory device is divided into multiple stacked layers, each containing memory cells and associated circuitry. This segmentation allows independent operation of each layer, enabling parallel access to different memory regions and reducing overall access time while maintaining high storage capacity through vertical stacking.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional stacked architecture. By adding the vertical dimension with multiple stacked layers, the system achieves higher storage capacity per unit area while incorporating through-silicon vias and interlayer connections that maintain fast access characteristics despite the increased depth.
2Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity is improved, but power consumption increases
Solution Approach 1:
Each stacked layer is equipped with independent word line driver circuits and bit line driver circuits, allowing selective activation of only the required memory layers. This segmentation enables the system to power down inactive layers, significantly reducing overall power consumption while maintaining high storage capacity across all layers.
Solution Approach 2:
The patent implements local driver circuits within each stacked layer rather than using centralized control. This allows each layer to be independently optimized and controlled, enabling precise power management where only the actively accessed layers consume significant power, while other layers remain in low-power states.
3Ease of manufacture
If conventional transistors are used in stacked memory, then manufacturing is simpler, but power consumption and access speed requirements are not met
Solution Approach 1:
The patent employs transistors with modified channel characteristics optimized for low-power operation in stacked memory configurations. By changing the transistor parameters such as threshold voltage and channel width-to-length ratio, the device achieves lower leakage current and reduced dynamic power consumption while maintaining compatibility with standard manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a memory device with lower power consumption and high storage capacity, suitable for applications requiring fast access times.
Implementation Method 1
incorporating a conductor that causes the spin Hall effect
Implementation Method 2
MTJ element, and the MTJ element includes a free layer
Data Source
AI summary
A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.