Memory Circuit Word Line Delay for Cross-Voltage Read Timing
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Solution Overview
Problem
The resistance of conductive lines in semiconductor integrated circuits (ICs) affects operating voltages and overall IC performance as ICs become smaller and more complex.
Innovation Solution
A memory circuit design that includes a level shifter circuit to delay the leading edge of the word line signal based on the voltage difference between supply voltages, reducing early read operations and improving performance by synchronizing the word line signal with the selection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the word line signal is activated immediately without delay, then the memory circuit responds faster to read operations, but early read operations occur causing performance degradation
Solution Approach 1:
The level shifter circuit performs preliminary action by delaying the word line signal activation before it reaches the memory cells. This delay ensures that the bit line voltage has fully stabilized before the word line is activated, preventing early read operations and improving overall circuit performance while maintaining responsive operation.
2Reliability
If the word line signal is delayed to prevent early read operations, then performance and static noise margin improve, but the response time increases
Solution Approach 1:
The level shifter circuit changes the timing parameter of the word line signal by introducing a controlled delay. This delay is specifically tuned to match the voltage swing characteristics and stabilization time of the bit line, ensuring optimal performance while minimizing the impact on overall response time.
3Use of energy by moving object
If different voltage supplies are used for different circuit sections, then voltage optimization is achieved, but voltage difference causes signal synchronization issues
Solution Approach 1:
The level shifter circuit acts as an intermediary between different voltage domains. It receives signals from the first voltage supply and transforms them to be compatible with the second voltage supply, ensuring proper signal synchronization and voltage optimization across different circuit sections.
Data Source
AI summary
A memory circuit includes a first and second inverter, a level shifter circuit, a memory cell configured to receive a word line signal, and a local input/output (LIO) circuit. The first inverter is coupled to a first voltage supply, and configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured generate a first and second signal responsive to a first or second input signal. The second inverter is configured to generate the word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first or second signal. An amount of delay of the leading edge of the word line signal is based on a voltage difference between the first and second supply voltage.