Ferroelectric Memory Cell Structure for Capacitance Control
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Solution Overview
Problem
Existing memory cells with ferroelectric films face limitations in microfabrication due to the inability to freely design area ratios among electrodes, leading to restricted capacitance and reliability issues from plasma exposure during manufacturing.
Innovation Solution
A semiconductor device with a nonvolatile memory cell structure that allows for independent control of the contact areas between ferroelectric and paraelectric films and electrodes, achieved through specific layer configurations and manufacturing processes that avoid plasma exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the area of the bottom electrode is increased to improve capacitance control, then the capacitance ratio between paraelectric and ferroelectric films can be adjusted, but the planar size of the memory cell increases
Solution Approach 1:
The patent transitions from planar electrode area adjustment to vertical stacking configuration. By forming the paraelectric film to extend over the side surface of the ferroelectric film in a stacked arrangement, the capacitance control is achieved through vertical dimension rather than horizontal area expansion, thus maintaining compact planar footprint while enabling flexible capacitance adjustment.
Solution Approach 2:
The patent divides the paraelectric film into distinct regions: a first region covering the upper surface of the bottom electrode, a second region covering the side surface of the ferroelectric film, and a third region covering the upper surface of the top electrode. This segmentation allows independent control of capacitance contributions from different spatial zones, enabling precise capacitance ratio adjustment without proportionally increasing overall planar area.
2Ease of manufacture
If conventional manufacturing processes are used with mask patterning, then electrodes can be formed, but the ferroelectric film is exposed to plasma causing reliability issues
Solution Approach 1:
The patent introduces a sacrificial mask layer that serves as an intermediary protective element during manufacturing. This mask layer is formed before depositing the ferroelectric film and is removed after ferroelectric film formation, preventing direct plasma exposure of the ferroelectric film while still enabling necessary electrode patterning operations to be performed.
Solution Approach 2:
The patent performs preliminary actions by forming the bottom electrode and paraelectric film structure before forming the ferroelectric film. The mask layer is established in advance to protect subsequent ferroelectric film deposition from plasma damage, and the sequence of operations is carefully orchestrated to minimize ferroelectric film exposure to harmful plasma environments.
3Adaptability or versatility
If the contact area between ferroelectric film and bottom electrode is decreased to adjust capacitance, then the paraelectric film capacitance can be increased, but the manufacturing precision requirements increase
Solution Approach 1:
The patent moves the capacitance control mechanism from the horizontal plane (contact area between electrodes) to the vertical dimension (side surface coverage). By extending the paraelectric film to cover the side surface of the ferroelectric film, the effective capacitance area can be adjusted through vertical thickness and lateral overhang control, which are more easily manufactured with standard precision than sub-micron horizontal alignment.
Solution Approach 2:
The patent applies different functional qualities to different regions of the paraelectric film: the first region provides bottom capacitance, the second region provides side surface capacitance with different dielectric properties, and the third region provides top capacitance. This local quality differentiation allows independent optimization of each region's contribution to total capacitance, enabling precise capacitance ratio control without requiring ultra-precise global alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances the performance and reliability of memory cells by enabling flexible capacitance adjustment without increasing planar size, while ensuring the ferroelectric film is not exposed to plasma, thus improving microfabrication and reliability.
Implementation Method 1
the amorphous HZO film is subjected to a heat treatment at 600 to 800° C. to form an orthorhombic HZO film
Implementation Method 2
the amorphous HZO film is subjected to a heat treatment at 600 to 800° C.
Implementation Method 3
the orthorhombic HZO film has ferroelectricity, the orthorhombic HZO film can be used as a ferroelectric film FE
Implementation Method 4
when a positive bias is applied to the top electrode TE, polarization in the ferroelectric film FE becomes downward
Data Source
AI summary
A performance of a memory cell including a ferroelectric film is improved. Reliability of the memory cell is ensured. A semiconductor device having a memory cell includes: a plurality of semiconductor layers configuring a channel region; a pair of semiconductor layers SI2 provided so as to sandwich the plurality of semiconductor layers SI1 in an X direction, connected to the plurality of semiconductor layers SI1, and configuring a source region and a drain region; a plurality of paraelectric films IL covering outer peripheries of the plurality of semiconductor layers SI1, respectively; a bottom electrode BE covering outer peripheries of the plurality of paraelectric films IL between the pair of semiconductor layers SI2; a ferroelectric film FE formed on the bottom electrode BE; and a top electrode TE formed on the ferroelectric film FE.