Dual-Side Bit Line Layout for Memory Array Signal Loss
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Solution Overview
Problem
The traditional approach of employing uniform-width bit lines on the frontside of memory cells in memory arrays fails to optimally address the varying performance demands of memory cells at different locations, leading to suboptimal performance due to increased resistance and parasitic capacitance.
Innovation Solution
Implementing a bit line structure with frontside and backside bit lines of varying widths, tailored to meet the unique requirements of memory cells at different distances from the input/output periphery, thereby optimizing circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform-width bit lines are used on the frontside of memory cells, then manufacturing simplicity is maintained, but resistance and parasitic capacitance increase leading to suboptimal performance
Solution Approach 1:
The patent applies local quality by varying the width of bit lines based on their specific location and function within the memory array. Frontside bit lines have different width characteristics than backside bit lines, and bit lines closer to I/O periphery have different specifications than those farther away. This localized differentiation optimizes signal transmission performance for each region while maintaining manufacturing feasibility through systematic design rules.
Solution Approach 2:
The patent introduces a new dimension to the bit line architecture by utilizing both frontside and backside of the memory array substrate. This dual-sided approach allows independent optimization of bit line characteristics on each side, effectively adding a spatial dimension to the design space. The backside bit lines can be engineered with different width profiles without constraining the frontside design, thereby reducing overall resistance and parasitic capacitance while maintaining manufacturing simplicity.
2Device complexity
If frontside bit lines with uniform width are deployed, then device complexity is reduced, but performance demands of memory cells at different locations are not met
Solution Approach 1:
The patent implements local quality by tailoring bit line width specifications to match the specific performance demands of memory cells at different locations. Frontside bit lines serving memory cells near the I/O periphery have optimized width characteristics, while backside bit lines serving distant cells have different characteristics. This location-specific optimization enhances memory array efficiency without introducing excessive complexity, as the variations follow systematic patterns rather than arbitrary designs.
Solution Approach 2:
The patent segments the bit line system into distinct frontside and backside components, each with independently optimized characteristics. This segmentation allows the memory array to be divided into functional zones with appropriate bit line specifications for each zone. The segmentation approach enables performance optimization for different location groups while maintaining manageable device complexity through modular design principles.
3Reliability
If bit lines are optimized for memory cells at specific locations, then signal transmission improves, but manufacturing complexity increases
Solution Approach 1:
The patent achieves local quality optimization through manufacturing-friendly design rules that systematicallly vary bit line widths based on location. Rather than requiring complex custom fabrication for each bit line, the design establishes clear patterns and guidelines for frontside versus backside bit lines, and for different regions within each side. This approach maintains ease of manufacture by using standard fabrication processes with location-based design parameters, while still achieving optimized signal transmission quality for memory cells at all locations.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cell are arranged in a row, and a first plurality of the memory cells are positioned closer to the logic cell than a second plurality of the memory cells. A frontside interconnect structure is disposed over the memory cells and includes a frontside bit line. The frontside bit line is coupled to each of the memory cells arranged in the row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. The backside bit line is coupled to at least the first plurality of the memory cells. The frontside bit line is coupled to the backside bit line through a source/drain feature of a pass-gate transistor of one of the first plurality of the memory cells.