Multilevel Resistive Memory Cell Using Dual Conductance States
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory (NVM) circuits using resistive memory devices are limited in bit density due to the inability to effectively utilize multiple resistance and conductance levels in memory cells.
Innovation Solution
A memory cell design that couples a resistive memory device in series with a switching device, allowing for programmable states corresponding to first and second resistance levels combined with first and second conductance levels, thereby increasing bit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistive memory devices are used with only two resistance levels, then the device structure remains simple, but the bit density is limited
Solution Approach 1:
The patent combines a resistive memory device with a switching device in a single memory cell to create a multi-state storage unit. The resistive memory device provides two resistance levels (high and low) while the switching device provides two conductance levels, creating four distinct programmable states. This merging allows the system to achieve higher bit density without proportionally increasing device complexity, as the combined structure functions as an integrated multi-level cell.
Solution Approach 2:
The patent utilizes parameter changes by exploiting both resistance levels (from the resistive memory device) and conductance levels (from the switching device) to create four distinct programmable states. By varying these electrical parameters, the memory cell can store multiple bits of information per cell, thereby increasing bit density without requiring additional physical memory cells.
2Quantity of substance
If multiple resistance levels are utilized in memory cells, then storage capacity increases, but the ability to reliably distinguish between states becomes more difficult
Solution Approach 1:
The switching device in the memory cell provides a controlled conductance path that enables selective access and measurement of the resistive memory device states. This feedback mechanism allows the read circuitry to precisely measure the combined resistance-conductance states, improving the ability to distinguish between the four programmable states while maintaining high storage capacity.
Solution Approach 2:
The switching device acts as an intermediary between the read circuitry and the resistive memory device. It controls the current flow through the resistive memory device, enabling precise measurement of the four distinct states (combining two resistance levels with two conductance levels) without directly measuring the resistive memory device alone, thereby improving state distinction accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory cell configuration enables increased bit density by reliably distinguishing between four programmable states, enhancing the storage capacity of NVM circuits.
Implementation Method 1
a resistive memory device configured to have a first resistance level in a first state and a second resistance level in a second state
Implementation Method 2
a switching device including a current path configured to, for a given input voltage level, have a first conductance level in a first programmed state and a second conductance level in a second programmed state
Data Source
AI summary
An integrated circuit (IC) device includes a first terminal, a second terminal, a resistive memory device configured to have a first resistance level in a first state and a second resistance level in a second state, and a switching device including a control terminal and a current path. The resistive memory device and the current path are coupled in series between the first and second terminals, and the switching device is configured to, responsive to a first voltage level at the control terminal, control the current path to have a first conductance level in a first programmed state and a second conductance level in a second programmed state.