Strong-Arm Comparator Calibration for 3D NAND Impedance Matching
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Solution Overview
Problem
The reduction in signal swing width due to increased operating speed in memory devices leads to impedance mismatch, causing signal reflection and reduced signal integrity, especially in high-speed data transmission, which is exacerbated by manufacturing process variations, supply voltage changes, and temperature fluctuations.
Innovation Solution
A calibration apparatus and method utilizing a strong-arm comparator and logic circuit to reduce comparison delay, allowing sufficient timing budget for impedance calibration, thereby improving signal integrity by reducing error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of the memory device is increased, then the data access and transmission speed is improved, but the signal swing width is reduced causing impedance mismatch and signal reflection
Solution Approach 1:
The patent performs impedance calibration before high-speed data transmission by comparing the impedance of data transmission paths with reference paths. The calibration apparatus adjusts termination resistors to match impedances in advance, ensuring that when high-speed transmission occurs, the impedance mismatch is already corrected, preventing signal reflection and maintaining signal integrity at high speeds
2Loss of time
If the signal swing width is reduced to increase transmission speed, then the delay time is reduced, but the signal transmission becomes greatly affected by external noise and impedance mismatch
Solution Approach 1:
The patent employs a feedback mechanism where the calibration apparatus continuously monitors impedance conditions by comparing data transmission paths with reference paths. Based on the comparison results, the system adjusts termination resistors to compensate for impedance variations caused by external noise and PVT changes, ensuring that even with reduced signal swing width, the signal remains immune to noise and impedance mismatch effects
3Reliability
If impedance calibration is performed to solve signal integrity issues, then the signal transmission quality is improved, but the calibration error rate increases due to insufficient timing budget
Solution Approach 1:
The patent segments the impedance calibration process into distinct phases: comparison phase where impedances are measured, latching phase where comparison results are captured, and adjustment phase where termination resistors are modified. By separating these functions and providing sufficient timing budget for each phase, the system achieves accurate impedance calibration without rushing the measurement process, thereby reducing calibration error rate while maintaining signal transmission quality
Data Source
AI summary
A calibration apparatus of a memory device and a calibration method thereof are provided. The memory device is a 3D NAND flash with high capacity and high performance. The calibration apparatus includes an impedance, a strong-arm comparator, a logic circuit, and a calibration controller. The impedance is configured to generate a comparison voltage. The strong-arm comparator includes a differential input pair and a latch. The differential input pair compares a reference voltage and the comparison voltage to produce a comparison result. The latch latches the comparison result and generates a latch signal and an inverted latch signal accordingly. The logic circuit generates a comparison result signal according to the latch signal and the inverted latch signal. The calibration controller implements an impedance calibration in the memory device according to the comparison result signal.