Sense Amplifier Layout With Dual ECC for Dense Memory Arrays
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Solution Overview
Problem
The increasing integration density of memory cells leads to higher probabilities of data errors due to interference and defects, necessitating complex and costly ECC circuits that occupy significant layout area and time for error correction.
Innovation Solution
A memory design with two ECC modules and sense amplifiers arranged on opposite sides of memory sections, connected to adjacent BLs, reducing interference and complexity by allowing separate error correction for adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single ECC module is used to check and correct errors in all sense amplifiers, then the error correction capability is comprehensive, but the ECC module complexity and layout area increase exponentially
Solution Approach 1:
The patent divides the ECC functionality into multiple independent ECC modules, each responsible for a specific subset of sense amplifiers. This segmentation reduces the complexity of each individual ECC module while maintaining comprehensive error correction capability across the entire memory device.
2Reliability
If more bits of errors are checked and corrected by the ECC circuit, then the error correction capability is enhanced, but the layout area and correction time increase exponentially
Solution Approach 1:
The patent segments the memory device into multiple regions with separate ECC modules, where each module handles a limited number of bits. This approach maintains comprehensive error correction while preventing exponential growth in layout area and correction time.
3Ease of repair
If redundant rows or columns are used to repair defects, then the repair capability is provided, but the repair range is limited and cannot handle high defect densities
Solution Approach 1:
The patent introduces ECC modules as intermediary components that work in conjunction with redundant rows or columns. The ECC modules perform preliminary error detection and correction, extending the effective repair range beyond what redundant rows or columns alone can achieve.
4Quantity of substance
If the integration density of memory cells is increased, then the memory capacity is improved, but the probability of data errors due to interference and defects increases
Solution Approach 1:
The patent divides the high-density memory into multiple regions, each with its own ECC module. This segmentation isolates errors to specific regions, preventing error propagation and maintaining reliability despite increased overall density.
Data Source
AI summary
The present disclosure provides a memory and a memory system thereof, relating to the technical field of semiconductors. The memory includes: memory sections and a plurality of bit lines (BLs) corresponding to a same memory section; sense amplifiers electrically connected to the plurality of BLs in one-to-one correspondence, where two of the sense amplifiers corresponding to adjacent two of the BLs are located on two sides of the memory section; and a first error checking and correction (ECC) module and a second ECC module, where one of two adjacent sense amplifiers located on a same side of the memory section is electrically connected to the first ECC module, and the other one of the two adjacent sense amplifiers located on the same side of the memory section is electrically connected to the second ECC module.