Multi-Storage-Row CIM Data Mapping for Fewer Buffer Fetches
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Solution Overview
Problem
Conventional multi-storage-row Compute-in-Memory (CIM) architectures suffer from inefficient memory use and suboptimal performance due to inflexible data mapping strategies, leading to redundant data handling and increased energy consumption, particularly in neural network layers with diverse characteristics.
Innovation Solution
Implement an adaptive data mapping protocol that dynamically reallocates data and operational sequences within a multi-storage-row CIM macro, utilizing customized peripheral circuits to optimize resource utilization and reduce redundant buffer accesses through shift-based data fetching and tailored memory interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed data mapping strategy is used in multi-storage-row CIM, then implementation simplicity is maintained, but memory utilization efficiency deteriorates and redundant data handling increases
Solution Approach 1:
The patent implements dynamic data mapping that adapts to different neural network layer characteristics. The system determines whether to use distributed mapping (multiple storage rows per layer) or concentrated mapping (single storage row per layer) based on the specific layer requirements, transforming the static fixed mapping into a dynamic adaptive mapping strategy that optimizes memory utilization while maintaining implementation feasibility
Solution Approach 2:
The patent changes the mapping parameters adaptively based on neural network layer characteristics. By adjusting the mapping configuration (distributed vs. concentrated) according to layer-specific requirements, the system optimizes memory access patterns and reduces redundant data handling, thereby improving productivity without significantly complicating the implementation
2Device complexity
If fixed data mapping strategy is used in multi-storage-row CIM, then system complexity is reduced, but energy consumption deteriorates due to redundant buffer accesses
Solution Approach 1:
The patent introduces dynamic data mapping that adapts to neural network layer characteristics, reducing redundant buffer accesses by optimizing data placement. This dynamic approach decreases energy consumption while maintaining manageable system complexity through systematic determination methods that select appropriate mapping strategies based on layer requirements
Solution Approach 2:
The patent changes mapping parameters adaptively to minimize redundant data handling and buffer accesses. By adjusting the mapping configuration based on layer characteristics, the system reduces energy-consuming operations while keeping the control mechanism systematic and manageable, balancing energy efficiency with system complexity
3Ease of operation
If fixed data mapping is used, then data access simplicity is maintained, but computational performance deteriorates due to suboptimal resource utilization
Solution Approach 1:
The patent implements dynamic data mapping that adapts to different neural network layer characteristics while maintaining systematic data access. The system determines the optimal mapping strategy (distributed or concentrated) based on layer requirements, achieving both improved computational performance through optimized resource utilization and maintained data access simplicity through structured access patterns
Solution Approach 2:
The patent changes mapping parameters adaptively based on neural network layer characteristics to optimize computational performance. By adjusting the mapping configuration (distributed vs. concentrated) according to layer-specific requirements, the system improves resource utilization and computational performance while maintaining systematic and simple data access through determined access patterns
Data Source
AI summary
A memory circuit includes an array, a first buffer, a fetch circuit, and a controller. The fetch circuit can be configured to fetch a first subset of a first data elements from the first buffer and temporarily store the first subset of the first data elements, during a first cycle to write the first subset of the first data elements to a first subset of a plurality of processing elements (PEs) arranged along a first one of rows in the array. The controller can be configured to control the fetch circuit to selectively limit fetching the first data elements from the first buffer.