Memory Processing Circuit with Enable-Gated Standby Leakage Control
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Solution Overview
Problem
Semiconductor memories face high power consumption due to significant leak currents in standby mode, particularly when low threshold voltage devices are used for speed, which can damage the circuit.
Innovation Solution
A circuit design that includes a receiving circuit, a first power supply circuit, and a processing circuit, where the power supply circuit controls the processing circuit's operating state based on an enable signal, ensuring it operates only when the signal is valid, thereby reducing leak current and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low threshold voltage devices are used to increase operating speed, then processing speed is improved, but leak current increases causing high power consumption and potential circuit damage
Solution Approach 1:
The patent implements dynamic control of the processing circuit by using an enable signal to switch between operational and standby states. The power supply circuit dynamically adjusts power delivery based on whether data processing is needed, allowing the system to use low threshold voltage devices for speed when active while preventing excessive leak current during standby periods.
Solution Approach 2:
The patent employs periodic enable signals to control the processing circuit's operational state. By periodically activating and deactivating the circuit based on data processing requirements, the system achieves high-speed processing when needed while minimizing power consumption during idle periods through controlled shutdown.
2Loss of time
If the processing circuit remains in operational state to maintain readiness, then response time is improved, but leak current increases causing excessive power consumption
Solution Approach 1:
The patent implements preliminary action by maintaining the processing circuit in a ready state only when necessary, using enable signals to pre-activate the circuit before data processing operations. This allows the system to minimize leak current during extended standby periods while ensuring rapid response when processing is actually required.
Solution Approach 2:
The system dynamically transitions the processing circuit between operational and standby states based on real-time requirements. The enable signal controls power supply to the processing circuit, creating a dynamic system that balances response time requirements against power consumption by being active only when data processing is needed.
3Duration of action of stationary object
If the processing circuit is continuously powered to reduce standby time, then availability is improved, but leak current causes circuit damage risk
Solution Approach 1:
The patent uses periodic enable signals to control power delivery to the processing circuit. By rhythmically activating and deactivating power based on data processing needs, the system maintains circuit availability when required while protecting against circuit damage during extended standby periods through controlled power reduction.
Solution Approach 2:
The system implements dynamic power management where the processing circuit transitions between fully powered, partially powered, and shutdown states. This dynamic approach maintains circuit reliability by preventing excessive leak current accumulation during standby while ensuring rapid activation when data processing operations are required.
Data Source
AI summary
A circuit for data processing includes a receiving circuit, a first power supply circuit and a processing circuit. The receiving circuit is configured to receive a data signal and determine a first node signal according to the data signal. The first power supply circuit is configured to receive an enable signal, and control, in a case that the enable signal is in a valid state, the processing circuit to be in an operating state. The processing circuit is configured to output, in a case of being in the operating state, a target data signal according to the first node signal.


