Vertical Resistive Memory Stack to Reduce Bias and Cell Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing resistive memory devices face challenges in reducing channel domination force and effective channel length, leading to increased bias requirements for program-erase operations and inter-cell interference.
Innovation Solution
A resistive memory device with a stack structure featuring alternately stacked interlayer insulating and conductive layers, a vertical hole with concave or semicircular sidewalls, and a gate insulating layer, channel layer, and variable resistance layer formed along these sidewalls, which reduces channel domination force and effective channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If variable resistance layers are formed close together in conventional resistive memory devices, then storage density is improved, but channel domination force increases and inter-cell interference occurs
Solution Approach 1:
The patent transitions from planar side-by-side variable resistance layer arrangement to a three-dimensional vertical stacking configuration. Multiple variable resistance layers are stacked vertically along the z-axis, separated by insulating layers, allowing high storage density while maintaining physical separation that prevents inter-cell interference.
2Length of moving object
If channel length is reduced to improve device scaling, then device density is improved, but channel domination force increases requiring higher bias
Solution Approach 1:
The channel region is segmented into multiple discrete sections by inserting insulating layers between consecutive variable resistance layers. This segmentation isolates each variable resistance layer's channel, reducing the cumulative channel domination force that would otherwise require higher bias voltages for program-erase operations.
3Ease of operation
If bias voltage is increased to overcome channel domination force, then program-erase operations are enabled, but energy consumption increases
Solution Approach 1:
Insulating layers are introduced as intermediary structures between variable resistance layers. These insulating layers act as barriers that reduce the electrostatic coupling and channel domination force between adjacent layers, thereby lowering the bias voltage required for program-erase operations and reducing overall energy consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure decreases the bias needed for program-erase operations and minimizes inter-cell interference by physically spacing apart variable resistance layers, enhancing operational efficiency.
Implementation Method 1
The ReRAM may store data according to a change in resistance of variable resistance layer. The variable resistance layer may be programmed to a high resistance state or a low resistance state according to voltages applied to the top electrode and the bottom electrode
Data Source
AI summary
There are provided a resistive memory device and a manufacturing method of the resistive memory device. The resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure in a vertical direction; and a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole.