3D Nanoribbon Hysteretic Memory for Higher Cell Density
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Solution Overview
Problem
Conventional hysteretic memory technologies face challenges in increasing memory density due to limitations in the number of front-end of line (FEOL) transistors that can be formed on a substrate, leading to diminishing returns and high process complexity, and the hysteresis loops of hysteretic materials often lack sharp transitions, making them susceptible to voltage disturbances.
Innovation Solution
Implementing vertically-stacked hysteretic memory using semiconductor nanoribbons, where memory cells are incorporated in multiple layers above a support structure, utilizing nanoribbon-based access transistors and capacitors with hysteretic materials or charge-trapping arrangements to enhance density and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked nanoribbon-based memory cells are implemented, then memory density is significantly increased and footprint area is reduced, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell layout to three-dimensional vertically-stacked architecture. Multiple memory cells are stacked along the vertical dimension using nanoribbon structures, allowing significant increase in memory density without proportionally increasing footprint area. This dimensional transition resolves the contradiction by exploiting the third dimension to pack more storage elements into the same planar space.
Solution Approach 2:
The patent implements nested structures where gate electrodes wrap around nanoribbon channels, and multiple functional layers (charge trapping layers, tunneling barriers, dielectric layers) are nested within each other vertically. This nesting approach allows compact integration of multiple memory cell components in the vertical direction, increasing density while maintaining a relatively compact device footprint.
2Quantity of substance
If conventional FEOL transistor scaling is continued, then memory density increases, but process complexity and manufacturing difficulty increase significantly with diminishing returns
Solution Approach 1:
The patent changes the fundamental structural parameters from planar transistors to vertically-oriented nanoribbon-based transistors. This parameter change enables continued scaling and density improvement without the exponential increase in process complexity associated with conventional planar transistor scaling. The vertical nanoribbon structure provides better electrostatic control and allows for more manageable fabrication processes at high density.
3Reliability
If hysteresis loops with sharp transitions are achieved, then susceptibility to voltage disturbances is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs composite material structures including charge trapping layers combined with tunneling barriers, and multiple dielectric layers with different properties. These composite structures create well-defined hysteresis loops with sharp transitions that provide noise immunity. The combination of different materials with complementary properties achieves the desired electrical characteristics without requiring extreme manufacturing precision in any single layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for significantly increased memory density and reduced footprint area while maintaining low power consumption and high endurance, addressing the scaling challenges of conventional FEOL memory technology.
Implementation Method 1
hysteretic memory refers to a memory technology employing hysteretic materials or arrangements
Implementation Method 2
Layers of different materials arranged in a stack to exhibit charge-trapping phenomena is one example of a hysteretic arrangement
Data Source
AI summary
Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.