Memory Bank Decoding Circuit Layout With Fewer Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional decoding circuits in semiconductor memory devices with multiple memory banks occupy a large space due to the need for a large number of transistors, limiting layout area and performance.
Innovation Solution
Replace conventional power supply voltage with memory-bank select signals and incorporate a discharge transistor to create a discharge path to the ground, reducing the number of transistors and space occupied by the decoding circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional decoding circuit is used to ensure only one memory bank is read or written at a time, then the memory operation reliability is improved, but the layout area is increased due to the large number of transistors required
Solution Approach 1:
The decoding circuit is segmented into multiple independent decoding circuits, each responsible for a specific memory bank. This segmentation allows each circuit to be minimized in size while collectively covering all memory banks, reducing the total area compared to a single large shared decoding circuit.
Solution Approach 2:
Each decoding circuit is designed to be multi-functional, handling both row decoding and column decoding operations for its assigned memory bank. This universality eliminates the need for separate dedicated decoding circuits for different operations, reducing the overall transistor count and layout area.
2Reliability
If a conventional decoding circuit with many transistors is used, then the memory bank selection reliability is improved, but the manufacturing cost is increased due to larger device complexity
Solution Approach 1:
The complex decoding function is segmented across multiple simplified decoding circuits, each handling a subset of memory banks. This segmentation reduces the complexity of each individual circuit while maintaining the overall reliability of memory bank selection through the collective operation of all segments.
Solution Approach 2:
Each decoding circuit is optimized with local quality principles, using transistor configurations and sizing specifically tailored to its assigned memory bank's requirements. This localized optimization reduces the overall device complexity compared to a uniform high-complexity design across all memory banks.
3Reliability
If a conventional decoding circuit occupying large space is used, then the memory bank selection reliability is improved, but the production cost is increased due to reduced layout efficiency
Solution Approach 1:
The decoding functionality is segmented into multiple compact circuits that can be efficiently packed in the layout. This segmentation improves manufacturing efficiency by allowing better utilization of the semiconductor wafer area, reducing the number of required fabrication steps, and lowering production costs compared to a single large decoding circuit.
Solution Approach 2:
The decoding circuits are arranged in a multi-dimensional layout configuration, utilizing both horizontal and vertical space efficiently. This dimensional arrangement increases layout density and manufacturing efficiency, reducing production costs while maintaining the reliability of memory bank selection.
Data Source
AI summary
Provided is a semiconductor memory device including a plurality of memory banks. Each of the memory banks includes a first memory cell, a second memory cell, a select circuit, and a decoding circuit. The select circuit is respectively coupled to the first and second memory cells through first and second bit lines, and selects the memory cell to be operated according to a first switch signal and a second switch signal. The decoding circuit generates the first switch signal and the second switch signal according to a memory-bank select signal, a first local column select signal, and a second local column select signal.