3D Memory Cell Structure With Threshold Switching Bit Line Contacts
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Solution Overview
Problem
Existing semiconductor devices with planar structures face challenges in achieving high integration and high capacity, particularly in memory technology, where three-dimensional structures are needed to meet the demands for reduced design rules and increased integration.
Innovation Solution
A semiconductor device with a three-dimensional cell structure is manufactured, featuring a substrate with word line structures, a switching layer, and bit line structures, where the switching layer performs a threshold switching operation with a variable programmable threshold voltage, and is fabricated through a method involving the formation of word line structures, interlayer insulation layers, and bit line contact holes filled with conductive material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If planar structure is used, then manufacturing process is simple, but integration degree and capacity are limited
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional vertical structure by stacking multiple functional layers (buffer layer, first semiconductor layer, second semiconductor layer, third semiconductor layer) in the thickness direction. This dimensional change enables increased integration degree and storage capacity while maintaining manufacturing feasibility through sequential layer formation processes
2Quantity of substance
If three-dimensional structure is implemented, then integration degree increases, but manufacturing precision requirements increase
Solution Approach 1:
The three-dimensional structure is segmented into distinct functional layers (buffer layer, first semiconductor layer, second semiconductor layer, third semiconductor layer) that can be formed and controlled separately. Each layer has specific thickness requirements and material compositions that can be independently optimized, reducing the overall manufacturing precision burden compared to a monolithic structure
Solution Approach 2:
The buffer layer is formed first as a preliminary structure to prepare the substrate for subsequent semiconductor layer deposition. This preliminary action establishes a controlled foundation that facilitates precise formation of subsequent layers with specific thicknesses and material properties
3Quantity of substance
If design rules are reduced, then device capacity increases, but manufacturing difficulty increases
Solution Approach 1:
By moving to a three-dimensional vertical architecture with stacked layers extending in the thickness direction, the patent achieves increased device capacity without requiring proportional reduction in lateral design rules. The vertical stacking provides additional degrees of freedom for increasing capacity while maintaining manufacturable lateral dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-dimensional structure enables high integration and high capacity, allowing for efficient threshold switching operations and reliable signal reading by varying threshold voltages, enhancing the performance of semiconductor devices.
Implementation Method 1
The switching layer may be configured to perform a threshold switching operation and have a variable programmable threshold voltage
Implementation Method 2
A conductive material may be provided in the bit line contact holes to form bit line structures
Data Source
AI summary
A method of manufacturing a semiconductor device comprises: providing a substrate having a base insulation layer; forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures; forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer; forming a plurality of second word line structures and a second switching functional layer disposed between the plurality of second word line structures; performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes; and providing a conductive material in the bit line contact holes to form bit line structures.