3D Variable Resistance Memory Strings for High-Density Fabrication

The patent implements a three-dimensional memory structure where memory cells are stacked vertically across multiple layers (first layer, second layer, third layer) with word lines extending in the third dimension perpendicular to the substrate. This vertical stacking achieves high integration density by utilizing the third spatial dimension rather than expanding only in the planar direction, thereby improving storage capacity per unit area while maintaining manufacturability through systematic layer formation processes.

The memory device is divided into multiple independently controllable layers, each with its own set of word lines (first word lines, second word lines, third word lines) that can be selectively activated. This segmentation allows individual layers or specific memory cells within layers to be accessed and operated independently, enabling faster write and read operations on selected cells without requiring erase operations on entire blocks, thus improving operation speed while maintaining reliability through selective access.

The patent combines multiple memory cells from different layers into a unified three-dimensional memory structure that shares common bit lines and control mechanisms. Memory cells in the first layer, second layer, and third layer are integrated with shared wiring infrastructure, reducing the total number of independent components and interconnections required. This merging approach achieves higher integration density while simplifying the overall device architecture and reducing processing costs through standardized fabrication processes.