Memory Control Signal Timing Using Word-Line Tracking Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-capacity memory devices, the control signal generator fails to activate modulation circuits at the correct timing due to varying arrival times of control signals across long word lines, leading to issues such as degraded read/write margins, increased crowbar current, and instability of bit cells.
Innovation Solution
The control signal generator adjusts its timing based on the depth distance between the first and last word lines, using tracking wiring to delay control signals appropriately, ensuring synchronized activation of modulation circuits with word line signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control signals are transmitted across long word lines in high-capacity memory devices, then memory capacity is increased, but control signals arrive at different times at different word lines causing timing errors
Solution Approach 1:
The patent applies preliminary action by delaying control signals in advance based on predicted propagation times. The control signal generator calculates expected arrival times at different word lines and pre-delays signals accordingly, so that all modulation circuits are activated simultaneously despite varying signal path lengths. This resolves the timing precision issue while maintaining high memory capacity.
Solution Approach 2:
The patent changes the timing parameter of control signals dynamically based on word line position. By adjusting the delay parameter proportionally to the depth distance from the first word line, the system compensates for signal propagation variations. This parameter adjustment ensures synchronized activation of modulation circuits across the entire memory array, resolving the timing error problem.
2Productivity
If modulation circuits are activated too early, then read/write operations can proceed, but read/write margins are degraded and crowbar current increases
Solution Approach 1:
The patent uses feedback by monitoring the actual arrival times of control signals at different word lines and adjusting the delay parameters accordingly. The control signal generator incorporates feedback about signal propagation characteristics to fine-tune the timing of modulation circuit activation. This ensures optimal timing that maintains read/write margins while enabling operations to proceed, resolving the contradiction between speed and reliability.
3Manufacturing precision
If control signals are delayed to synchronize modulation circuit activation, then timing precision is improved, but signal transmission complexity increases
Solution Approach 1:
The patent applies local quality by implementing different delay amounts for different word lines based on their specific positions. Rather than using a uniform delay for all signals, the system tailors the delay parameter to each word line's depth distance from the first word line. This localized approach achieves precise synchronization while minimizing overall system complexity, as each delay is optimized only for its specific context.
Data Source
AI summary
A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.