Cell-on-Periphery Memory Core Layout for Smaller DRAM Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM devices face challenges in reducing size due to limitations in circuit arrangements, particularly with vertical channel transistors, as the size reduction is often limited by the circuits driving the memory cell array.
Innovation Solution
A memory core circuit and device design utilizing a cell-on-periphery (CoP) structure, where a core control circuit is disposed underneath a memory cell array, efficiently arranging sub peripheral circuits, including sub wordline drivers, bitline sense amplifiers, row decoding circuits, power circuits, and control circuits in a matrix layout, enhancing design margins and operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical channel transistor structure is employed to reduce memory device size, then device area is reduced, but the size reduction is limited by the driving circuits
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional stacked architecture where memory cell arrays are positioned above the core control circuit. This vertical stacking enables the memory device to achieve size reduction by utilizing the third dimension (height) rather than only the planar area, effectively overcoming the limitation imposed by driving circuit footprint.
Solution Approach 2:
The memory device is divided into distinct functional layers: memory cell arrays positioned above and core control circuits positioned below. This segmentation allows independent optimization of each layer and enables efficient space utilization by placing high-density memory cells in the upper layer while housing control logic in the lower layer, thereby reducing overall device footprint.
2Area of moving object
If core control circuit is disposed underneath memory cell array, then area utilization is improved, but circuit arrangement complexity increases
Solution Approach 1:
The core control circuit layer is designed to perform multiple functions including row decoding, column decoding, sense amplification, and bit line/word line driving. By integrating these diverse functions into a unified core control layer positioned beneath the memory cell arrays, the patent achieves efficient area utilization while managing complexity through functional integration rather than separate discrete circuits.
Solution Approach 2:
The patent resolves the area utilization versus complexity contradiction by moving the core control circuit to a different spatial dimension (below the memory cell array) rather than competing for planar space. This vertical separation allows the control circuit to access and control the memory cell array through vertical interconnects, simplifying the horizontal circuit arrangement while maximizing area efficiency.
Data Source
AI summary
A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.