Crossbar Array Input Shaping for Unselected RRAM Disturbance

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Solution Overview

Problem

Crossbar array circuits experience significant disturbances during in-memory computing operations, particularly during Vector-by-Matrix-Multiplication (VMM) operations, due to parasitic capacitance leading to unintended programming of unselected RRAM devices and increased computational errors.

Innovation Solution

Implementing a slew rate controller to transform step function input signals into slew rate input signals, reducing voltage peaks and exponential decay of disturbance voltages across unselected RRAM devices, thereby minimizing interference between selected and unselected devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If step function input signals are used in crossbar array circuits, then switching speed is improved, but disturbance voltage peaks occur causing unintended programming of unselected RRAM devices

Engineering Contradiction:
Improveswitching speedVSAvoiddisturbance voltage peaks
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The slew rate controller pre-shapes the input signal by gradually ramping up the voltage before the actual switching event, preventing sudden voltage peaks that would cause disturbance to unselected devices while maintaining fast switching performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the temporal profile parameter of the input signal from a step function to a slew-rate-limited waveform, controlling the rate of voltage change to eliminate harmful voltage peaks while preserving switching speed

Inventive Principle:
Principle #35Parameter changes

2Productivity

If high voltage is applied to selected RRAM devices for programming, then programming efficiency is improved, but disturbance to unselected devices increases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidinterference to unselected devices
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The slew rate controller acts as an intermediary between the voltage source and the crossbar array, filtering and shaping the voltage waveform to deliver high voltage to selected devices while preventing harmful voltage transients from reaching unselected devices through parasitic capacitance coupling

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If fast switching is implemented in crossbar arrays, then computational speed is improved, but computational errors increase due to disturbance

Engineering Contradiction:
Improvecomputational speedVSAvoidcomputational accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

By pre-shaping the voltage waveform through slew rate control before the switching event, the system eliminates disturbance-induced errors while maintaining fast switching, thereby improving both speed and reliability simultaneously

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of a slew rate controller reduces disturbances and computational errors in large-scale crossbar array circuits by controlling voltage fluctuations, enhancing flexibility and scalability.

Implementation Method 1

a slew rate controller connected to the DACs, wherein the slew rate controller is configured to receive an input signal

Methodology Applied
Scientific EffectSlew rate control:

Data Source

PatentUS12475947B2Reducing disturbance in crossbar array circuits
Publication Date: 2025.11.18 TETRAMEM INC
  • US12475947B2 patent drawing
  • US12475947B2 patent drawing
  • US12475947B2 patent drawing

AI summary

A crossbar circuit is provided. The crossbar circuit includes one or more bit lines, one or more word lines, one or more cell devices connected between the bit lines and the word lines, one or more analog-to-digital converters (ADCs) connected to the one or more bit lines, one or more digital-to-analog converters (DACs) connected to the one or more word lines, one or more access controls connected to the one or more cell devices and configured to select a cell device in the one or more cell devices and to program the selected cell device, and a slew rate controller connected to the one or more bit lines. The first slew rate controller is configured to receive an input signal or a bias and output a slew-rate controlled signal.