SRAM Word Line Underdrive With Process-Temperature Compensation
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Solution Overview
Problem
Existing SRAM architectures face challenges in maintaining high bitcell stability and read/write speed while minimizing power consumption, particularly in low voltage applications, due to variations in process corners and temperature, which affect the static noise margin (SNM) and word line underdriving levels.
Innovation Solution
A SRAM architecture that utilizes a PMOS transistor as a word line underdrive with a temperature and process-compensated gate voltage, combined with a negative bias generation circuit to control the gate of the underdrive transistor, ensuring consistent underdriving levels across various process and temperature conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the supply voltage is used to power the word lines in smaller transistor memory cells, then the read/write speed is improved, but the static noise margin (SNM) is degraded
Solution Approach 1:
The patent implements dynamic word line underdriving by controlling the switch (third transistor) to connect the underdrive transistor to the word line only during specific operations (read or write). This dynamic activation allows the system to achieve speed improvement during active operations while maintaining stability during idle periods, resolving the contradiction between speed and noise margin
Solution Approach 2:
The patent changes the electrical parameters of the word line by introducing an underdrive voltage through the underdrive transistor. This underdriving effect modifies the effective voltage on the word line, reducing noise coupling to the bitcells and improving static noise margin while maintaining adequate drive strength for fast read/write operations
2Area of stationary object
If the size of the underdrive transistor is reduced to minimize area usage, then the area consumption is decreased, but the underdrive control effectiveness is reduced
Solution Approach 1:
The patent applies preliminary anti-action by using the switch (third transistor) to preemptively connect the underdrive transistor to the word line before the main word line activation. This early connection establishes the underdriving effect in advance, ensuring that even a small underdrive transistor can effectively control noise margins when properly timed, thereby maintaining effectiveness while minimizing area
Solution Approach 2:
The underdrive transistor operates periodically rather than continuously, activated only during read or write operations through the clocked switch. This periodic activation allows the smaller underdrive transistor to concentrate its effect during critical operations, maintaining control effectiveness while reducing the required transistor size and area
3Device complexity
If process and temperature variations are not compensated, then the device complexity is reduced, but the bitcell stability varies across different conditions
Solution Approach 1:
The patent implements self-service by using dummy bitcells that automatically track and compensate for process and temperature variations. These dummy cells experience the same environmental conditions as the actual bitcells and generate compensation signals that automatically adjust the underdriving level, providing adaptive stability without requiring complex external compensation circuits
Solution Approach 2:
The patent establishes a feedback mechanism where the dummy bitcells monitor process and temperature conditions and use this information to dynamically adjust the underdrive transistor control. The feedback loop ensures that the underdriving effect adapts to varying conditions, maintaining bitcell stability across different process corners and temperatures while keeping the overall device complexity manageable
Data Source
AI summary
Disclosed herein is an electronic device, including a plurality of row decoders. Each row decoder includes decoder logic generating an initial word line signal and word line driver circuitry generating an inverse word line signal at an intermediate node from the initial word line signal, and generating a word line signal at a word line node from the inverse word line signal. A word line underdrive p-channel transistor has a source coupled to the intermediate node, a drain coupled to a word line underdrive sink, and a gate controlled based upon the inverse word line signal. Negative bias generation circuitry generates the negative bias voltage at a gate of the word line underdrive p-channel transistor when the initial word line signal is at a logic high, and couples the gate of the word line underdrive p-channel transistor to ground when the initial word line signal is at a logic low.