Distributed MRAM Array Layout With Shared Read-Write Circuits
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Solution Overview
Problem
Existing memory architectures occupy more layout area than desired, limiting the number of devices that can be included on each integrated circuit chip.
Innovation Solution
Implementing a memory device with shared read and write circuits for magnetic tunnel junction (MTJ) bits, allowing the array circuit to be powered off between operations, thereby reducing layout area and enabling more devices per chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory architecture with dedicated read and write circuits for each MTJ bit is used, then reliable read and write operations are achieved, but layout area increases significantly
Solution Approach 1:
The patent implements shared read and write circuits that serve multiple MTJ bits simultaneously. The read circuit and write circuit are designed to be universally applicable across different MTJ bits within the array, eliminating the need for dedicated circuits for each bit. This multi-functional approach significantly reduces the layout area while maintaining the reliability of read and write operations through proper circuit sharing mechanisms.
Solution Approach 2:
The patent merges the read circuit and write circuit into a shared infrastructure that serves the entire MTJ array. By combining these functions at the circuit level and allowing them to be shared across multiple bits, the overall layout area is reduced. The merging is achieved through careful design of shared bit lines, word lines, and control logic that can handle both read and write operations for multiple MTJ bits.
2Productivity
If more MTJ bits are included on each integrated circuit chip to increase speed and performance, then processing speed and performance improve, but layout area constraints are violated
Solution Approach 1:
By implementing universal read and write circuits that can serve multiple MTJ bits, the patent enables a higher density of MTJ bits on the chip. The shared circuits reduce the overhead area per bit, allowing more functional bits to be packed into the available layout area, thereby increasing overall processing speed and performance.
Solution Approach 2:
The patent segments the memory array into multiple MTJ bits that can be independently addressed and accessed through the shared read and write circuits. This segmentation allows for parallel access to multiple bits while using a common circuit infrastructure, effectively increasing productivity without proportionally increasing the layout area.
3Speed
If array circuit remains powered on continuously to enable fast access, then access speed improves, but power consumption increases
Solution Approach 1:
The patent implements periodic powering of the array circuit, where the circuit is powered on only during read or write operations and powered off during idle periods. The shared read and write circuits enable this periodic operation by efficiently managing power states across the entire array, reducing overall power consumption while maintaining fast access speeds when needed through rapid circuit activation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances area efficiency by allowing simultaneous reading and writing of multiple MTJs, reducing power consumption and layout area, and enabling faster response times.
Implementation Method 1
a first array of at least two MTJs having a first polarity and a second array of at least two MTJs having a second polarity opposite the first polarity
Implementation Method 2
a read device configured to read the first polarity of the at least two MTJs of the first array, the read device configured to read the second polarity of the at least two MTJs of the second array
Implementation Method 3
a write circuit electrically connected to the MTJ bit, wherein the write circuit is configured to write the MTJs in the first array and the second array
Data Source
Figure 1~2
Figure 3A
Figure 3B
AI summary
A memory device including an array circuit including a magnetic tunnel junction (MTJ) bit having a logical state and including a set of MTJs is provided. The memory device further includes a read device electrically connected to the MTJ bit and configured to read the logical state of the MTJ bit. The memory device includes a write circuit electrically connected to the MTJ bit and configured to write the logical state of the MTJ bit. The array circuit is powered off between operations on the MTJ bit by the read device and/or the write circuit.