Memory Command Pin Segmentation for Faster Bank Interleave
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Solution Overview
Problem
Existing memory devices face challenges in efficiently managing high-capacity and high-bandwidth data processing, particularly in electronic devices like smartphones and AI accelerators, due to the need for an efficient input and output interface method between host devices and memory controllers.
Innovation Solution
A memory device design that includes separate row and column pins for receiving commands, allowing for specific commands to be received at precise edges of a clock signal, such as active and precharge commands, to optimize command timing and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If commands are received through a single interface method, then the interface structure is simple, but the operational speed and command execution efficiency are limited
Solution Approach 1:
The command interface is segmented into separate row pins and column pins, each dedicated to specific command types. Row pins receive row commands (activate, precharge) while column pins receive column commands (read, write), enabling parallel command processing and improving execution speed without creating a monolithic complex interface
Solution Approach 2:
The patent introduces a two-dimensional command reception structure with separate row and column pin groups, transforming the traditional single-dimension command interface. This dimensional separation allows simultaneous command reception on different pin groups, enhancing throughput while maintaining manageable interface complexity
2Loss of time
If commands are received during full clock cycles, then the timing is relaxed and easier to implement, but the latency and operational efficiency increase
Solution Approach 1:
Command reception is synchronized to specific edges of the clock signal (rising or falling edges) rather than requiring full clock cycle completion. This periodic sampling approach reduces command latency by allowing immediate recognition at clock edges while maintaining implementation simplicity through regular timing intervals
Solution Approach 2:
The interface circuit is designed to receive and latch commands at specific clock edges in advance of full cycle completion. By preparing to receive commands at predetermined timing points (rising or falling edges), the system reduces latency without requiring complex timing control during operation
3Productivity
If all commands are received through row pins, then the pin assignment is simple, but the command processing parallelism and throughput are limited
Solution Approach 1:
The pin assignment is segmented into row pins for row commands and column pins for column commands. This segmentation enables parallel command processing where different command types can be received simultaneously on different pin groups, increasing throughput while keeping each pin group's assignment relatively simple
Solution Approach 2:
Each pin group (row pins and column pins) is designed with multi-functionality to handle different command types appropriate to its category. Row pins universally handle all row-related commands (activate, precharge) while column pins handle all column-related commands (read, write), providing flexibility without requiring complex individual pin assignments
Data Source
AI summary
A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.