Word Line Test Circuit for Metal Line Resistance Defects

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Solution Overview

Problem

Existing semiconductor devices face challenges in detecting defects in metal lines, particularly due to increased resistance values that affect the speed of signal transmission, leading to potential defects and operational delays.

Innovation Solution

Incorporation of a test mode control circuit that monitors the resistance value of metal lines and adjusts the driving of the metal lines based on the detected resistance, maintaining or disabling the signal state as necessary to prevent defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the metal line is used to transmit the main word line signal in normal operation, then the signal transmission function is achieved, but defects such as increased resistance values may occur that affect transmission speed

Engineering Contradiction:
Improvemetal line defect detectionVSAvoidtest mode control circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test mode control circuit performs preliminary detection of metal line defects by monitoring resistance values before they affect normal operation. The circuit proactively identifies potential issues by comparing resistance measurements against threshold values, preventing defects from escalating into operational failures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The test mode control circuit acts as an intermediary between the metal line and the control logic. It interfaces with the metal line through resistance measurement and translates physical defect conditions into actionable test mode signals, enabling indirect detection without disrupting normal signal transmission.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the test mode control circuit monitors resistance values continuously, then defect detection precision is improved, but energy consumption increases

Engineering Contradiction:
Improveresistance value detectionVSAvoidtest mode control circuit energy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The test mode control circuit performs resistance measurements periodically rather than continuously. It enters test mode at specific intervals or under predetermined conditions, achieving sufficient detection precision while minimizing energy consumption by keeping the measurement function dormant during normal operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit changes its operational parameters by switching between normal mode and test mode. During test mode, it measures resistance values with high precision; during normal mode, it operates with minimal energy consumption. This parameter switching allows the system to achieve high measurement precision only when necessary.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the test mode control circuit drives the metal line to maintain signal state, then operational failures are prevented, but the complexity of control logic increases

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoidcontrol logic
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test mode control circuit uses feedback from resistance value measurements to control its driving actions. When the measured resistance exceeds a threshold, the circuit activates test mode and drives the metal line to maintain the signal state. This feedback-based control achieves high reliability while keeping the control logic relatively simple and intuitive.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12475962B2Semiconductor device providing a test mode related to detecting a defect in a metal line
Publication Date: 2025.11.18 SK HYNIX INC
  • US12475962B2 patent drawing
  • US12475962B2 patent drawing
  • US12475962B2 patent drawing

AI summary

A semiconductor device including a main word line driver connected to a metal line and configured to transmit a main word line signal to the metal line in order to access at least one of memory cells that are included in a core circuit, the core circuit connected to the metal line and configured to transmit, as a delay main word line signal, the main word line signal that is received through the metal line. The semiconductor device including a test mode control circuit connected to the metal line. The test mode control circuit configured to receive the delay main word line signal through the metal line. The test mode control circuit configured to perform a test mode in which the test mode control circuit drives the metal line in response to the delay main word line signal.