2Read/2Write Register File Array Sub-Array Partitioning
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Solution Overview
Problem
Conventional register file arrays require large SRAM cell areas and complex decoding schemes to support multiple simultaneous reads and writes, leading to slow access times and increased area usage.
Innovation Solution
A 2Read/2Write register file array is partitioned into sub-arrays with each sub-array containing 16 entries, allowing for multiple simultaneous reads and writes using only one read address and one write address, with a simplified decoding scheme that reduces the number of address decodes required from 6 to 4, enabling efficient alignment and access of consecutive entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional register file array uses multiple read/write ports to support multiple simultaneous reads and writes, then the number of simultaneous operations increases, but the SRAM cell area and decoding complexity increase significantly
Solution Approach 1:
The register file array is divided into multiple sub-arrays (e.g., 4 sub-arrays of 16 entries each). Each sub-array can be independently accessed, allowing multiple simultaneous operations across different sub-arrays while keeping each sub-array compact and efficient
Solution Approach 2:
The patent introduces a sub-array selection dimension in addition to the traditional address dimension. By selecting which sub-arrays are active and using alignment logic to map logical addresses to physical sub-array positions, the system achieves multiple simultaneous operations without proportionally increasing the area of individual SRAM cells
2Productivity
If a conventional register file array uses multiple read/write ports to support multiple simultaneous reads and writes, then the number of simultaneous operations increases, but the decoding complexity increases
Solution Approach 1:
The address decoding is segmented into two stages: first decoding the sub-array index to select which sub-arrays are active, then decoding the offset within each sub-array. This divides the complex single-stage decoding into simpler, modular stages that can be implemented more efficiently
Solution Approach 2:
The patent performs preliminary alignment of addresses to determine which sub-arrays will be accessed before the actual read/write operations. This pre-computation of sub-array selection simplifies the subsequent decoding required during the actual memory access operations
3Productivity
If a conventional register file array uses a large SRAM cell area to support multiple simultaneous reads and writes, then the number of simultaneous operations increases, but the access time increases
Solution Approach 1:
By segmenting the large register file into smaller sub-arrays, each sub-array can be accessed more quickly than a single large array. The segmented structure reduces the critical path for address decoding and data access within each sub-array, improving overall access time despite supporting multiple simultaneous operations
Data Source
AI summary
Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.