Register Arrangements TRIZ Cases
- Dynamic Counter Pool Allocation for Register Mapping Tracking
A mapper unit assigns counters from a shared pool to track logical register mappings to physical registers.
- Packed Data Operation Mask Concatenation for SIMD Throughput
Concatenating packed data operation masks improves instruction throughput and code density in SIMD architectures without increasing processor complexity.
- Scalable Parallel Processing via Thread Array Grids
Thread array grids distribute tasks across available cores, eliminating code modifications for varying hardware configurations.
- Neural Network Performance Monitoring via Label-Based PMU Counting
Label-based performance monitoring units count neural network events without reconfiguring hardware between layers, preserving processing speed.
- Hardware-Assisted Heterogeneous ISA Dispatcher for Core Utilization
A hardware-assisted heterogeneous ISA dispatcher enables dynamic switching between instruction set architectures across processor cores.
- MEMV Register File Access for Vector Processor Bandwidth
A DMA controller arranges vector elements across memory banks to enable parallel multi-element access in vector processors.
- Tensor Permutation Engine Address Generation for Cache Line Transfers
A Tensor Permutation Engine generates read and write addresses using bit permutations to move tensor data elements through shuffle register banks.
- Dynamic Architectural Register Mapping for Physical Pool Optimization
Dynamic configuration reduces architectural registers to increase the physical register pool, resolving area and power constraints during register renaming.
- VLIW Compiler Register Allocation for Distributed DSP
Compiler identifies data sharing relations to allocate registers in distributed VLIW DSP processors, reducing communication overhead.
- Context Buffer and Register Management for Thread Latency Prediction
A processing device moves context information between registers and a context buffer based on predicted thread latencies.
- FP8 Classification Instructions for ML Precision and Memory
FP8 classification instructions extract exponents and mantissas to accelerate matrix compute operations while resolving precision and memory trade-offs.
- Speculative Register File Read Suppression Circuit
Read suppression circuitry maintains a boundary pointer to suppress unnecessary reads in speculative register files, reducing processor power consumption.
- SIMT Register File Allocation via Mapping Table Parsing
A register file mapping table parses available entries to associate pointers with physical addresses for thread group allocation.
- Horizontal Vector Instruction With Independent Read And Write Masks
A horizontal vector instruction uses independent read and write masks to process selected elements.
- Configurable Register Files for Test Signature Generation
A configurable register file operates as general-purpose registers during normal processing and reconfigures to accumulate test data in test mode.
- Mask Register Bit Reversal and Permutation Instructions
New instructions reverse and permute mask register bits, resolving performance limits in parallel vector operations.