Dynamic Architectural Register Mapping for Physical Pool Optimization
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Solution Overview
Problem
Existing data processing systems face challenges in increasing the number of physical registers available for register renaming without increasing the overall size of the physical register set, which is constrained by design factors like area and power consumption, and require modifications to the operating system or applications to utilize unused registers effectively.
Innovation Solution
The solution involves using configuration storage to dynamically modify configuration data during operation, allowing the processor to reduce the number of architectural registers that need to be mapped to physical registers, thereby increasing the pool of available physical registers without requiring additional physical registers or modifications to the operating system or applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of physical registers is increased to improve register renaming performance, then the number of available physical registers for mapping increases, but the area and power consumption of the design increase
Solution Approach 1:
The patent implements dynamic configuration of the architectural register set size through configuration storage that can be modified during operation. The processor can switch between different sizes of architectural register sets (e.g., 31 registers vs. 16 registers) depending on the software hierarchical level being executed, allowing the physical register pool to be dynamically optimized for different operating modes without permanently increasing the physical register set size
2Productivity
If the number of physical registers is increased to improve register renaming performance, then the number of available physical registers for mapping increases, but the power consumption of the design increases
Solution Approach 1:
The configuration storage allows the processor to dynamically adjust the architectural register set size based on the executing software level, thereby dynamically optimizing power consumption. When executing at lower hierarchical levels (e.g., application level), a smaller architectural register set (16 registers) is used, freeing more physical registers for renaming and reducing power consumption compared to maintaining a full 31-register architectural set at all times
3Productivity
If the architectural register set size is reduced to increase the pool of available physical registers, then more physical registers are available for mapping, but the adaptability to different software requirements decreases
Solution Approach 1:
The patent employs dynamic reconfiguration capability where the architectural register set size can be changed during operation based on the software hierarchical level. Configuration storage holds data that defines the current architectural register set size, allowing the processor to adapt between 31 registers for full software compatibility and 16 registers for optimized performance, thereby maintaining both adaptability and productivity
Solution Approach 2:
The invention changes the parameter of architectural register set size dynamically based on operating mode. By modifying the configuration data in configuration storage, the processor can switch between different register set sizes (31 vs. 16 registers), allowing optimization of the physical register pool for renaming while maintaining software compatibility when needed
Data Source
AI summary
An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers.