Tensor Permutation Engine Address Generation for Cache Line Transfers
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Solution Overview
Problem
Current methods for tensor transformations in machine learning workloads, such as those involving neural networks, are inefficient due to significant overhead from instruction calls and strided data access, especially when dealing with large tensors, leading to suboptimal performance in data movement within the cache hierarchy.
Innovation Solution
A Tensor Permutation Engine (TPE) is introduced, which uses bit permutations to procedurally generate read and write addresses for tensor rotations, allowing full cache line transfers without partial updates and maintaining high bandwidth, thereby optimizing tensor reorganization operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector instructions are used for tensor transformations, then the transformations can be performed, but the number of instruction calls increases significantly leading to overhead
Solution Approach 1:
The tensor transformation operation is segmented into distinct phases: address generation using bit permutations, data gathering, and data scattering. This segmentation allows each phase to be optimized independently, reducing the overhead of instruction calls by consolidating operations within each phase.
Solution Approach 2:
Address generation is performed preliminarily using bit permutation logic before the actual data movement occurs. By pre-calculating source and destination addresses through bit manipulation, the system avoids the overhead of computing addresses during data movement, thus reducing instruction call overhead.
2Productivity
If scatter/gather methods are used to rotate tensor elements, then the elements can be rearranged, but strided data access increases leading to additional overhead
Solution Approach 1:
The system changes the access pattern parameter from strided access to sequential cache line access. By using bit permutations to generate addresses that map to sequential cache line transfers, the system eliminates the overhead associated with strided access while maintaining the ability to rearrange tensor elements effectively.
3Manufacturing precision
If partial cache line updates are performed, then precise tensor element placement is achieved, but bandwidth efficiency decreases
Solution Approach 1:
The system performs excessive action by transferring full cache lines even when only部分 elements are needed for the current transformation step. This approach trades some redundant data transfer for significantly improved bandwidth utilization and reduced overhead, as full cache line transfers are more efficient than partial updates.
Data Source
AI summary
An apparatus and method for a tensor permutation engine. The TPE may include a read address generation unit (AGU) to generate a plurality of read addresses for the plurality of tensor data elements in a first storage and a write AGU to generate a plurality of write addresses for the plurality of tensor data elements in the first storage. The TPE may include a shuffle register bank comprising a register to read tensor data elements from the plurality of read addresses generated by the read AGU, a first register bank to receive the tensor data elements, and a shift register to receive a lowest tensor data element from each bank in the first register bank, each tensor data element in the shift register to be written to a write address from the plurality of write addresses generated by the write AGU.