SIMT Register File Allocation via Mapping Table Parsing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

State-of-the-art graphics processors experience allocation fragmentation in register files due to variable execution orders of thread groups, leading to inefficient allocation of registers using traditional linear schemes and FIFO techniques.

Innovation Solution

A system and method for efficient register file allocation using a memory management unit (MMU) that employs a register file mapping table (RFMT) to allocate register file entries to thread groups, parsing the table to locate available entries and associate pointers with corresponding register file addresses, optimizing allocation through 4S and 2S region management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a linear register file allocation scheme using FIFO technique is used, then the allocation process is simple to implement, but allocation fragmentation occurs when thread groups terminate early, reducing memory utilization efficiency

Engineering Contradiction:
Improveimplementation simplicityVSAvoidmemory utilization efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The register file is divided into multiple banks, and a mapping table is introduced to segment the allocation management. Each bank can be independently managed, allowing parallel allocation operations and reducing fragmentation by distributing thread groups across different banks based on availability rather than strict linear order.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A mapping table is introduced as an intermediary data structure between the thread groups and the physical register file banks. This mapping table tracks the allocation state of each bank and enables the allocator to make informed decisions about where to place new thread groups, avoiding fragmented regions and improving overall memory utilization while maintaining allocation simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If traditional linear allocation schemes are used, then the allocation logic is straightforward, but the speed of memory allocation decreases due to fragmentation and the need to search for contiguous blocks

Engineering Contradiction:
Improveallocation logic complexityVSAvoidmemory allocation speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The system performs preliminary actions by pre-organizing register file banks into allocatable units and maintaining a mapping table that pre-calculates and tracks the availability status of each bank. When a thread group needs allocation, the system can quickly query the pre-prepared mapping table to find suitable banks without performing complex searches or dealing with fragmentation issues, thereby increasing allocation speed while keeping logic manageable.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If register files are allocated to thread groups based on variable execution orders, then the system can handle diverse workloads efficiently, but allocation fragmentation increases, wasting register file space

Engineering Contradiction:
Improveworkload handling capabilityVSAvoidregister file space waste
Core Design Contradiction:
Adaptability or versatilityVSLoss of substance

Solution Approach 1:

The register file allocation system is made dynamic by introducing a mapping table that can be updated in real-time as thread groups are allocated and deallocated. The mapping table dynamically tracks which banks are available and which are occupied, allowing the system to adapt to variable workload execution orders while minimizing fragmentation by always directing new allocations to the most suitable available banks rather than following a fixed linear pattern.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9798543B2Fast mapping table register file allocation algorithm for SIMT processors
Publication Date: 2017.10.24 NVIDIA CORP
  • US9798543B2 patent drawing
  • US9798543B2 patent drawing
  • US9798543B2 patent drawing

AI summary

One embodiment of the present invention sets forth a technique for allocating register file entries included in a register file to a thread group. A request to allocate a number of register file entries to the thread group is received. A required number of mapping table entries included in a register file mapping table (RFMT) is determined based on the request, where each mapping table entry included in the RFMT is associated with a different plurality of register file entries included in the register file. The RFMT is parsed to locate an available mapping table entry in the RFMT for each of the required mapping table entries. For each available mapping table entry, a register file pointer is associated with an address that corresponds to a first register file entry in the plurality of register file entries associated with the available mapping table entry.